Fast neural decoders for some cyclic codes

Yuen Hsien Tseng; Ja Ling Wu

doi:10.1080/00207219308907135

Fast neural decoders for some cyclic codes

Yuen Hsien Tseng, Ja Ling Wu

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

A number of cyclic and BCH code decoders that have 0(1) time complexity and less hardware complexity than conventional digital decoders are presented. The neural decoder is formulated as a set of parity networks in the first layer followed by a linear perceptron in the second layer, and thus has simple implementation in VLSI technology.

Original language	English
Pages (from-to)	595-600
Number of pages	6
Journal	International Journal of Electronics
Volume	75
Issue number	4
DOIs	https://doi.org/10.1080/00207219308907135
Publication status	Published - 1993 Oct
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1080/00207219308907135

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title = "Fast neural decoders for some cyclic codes",

abstract = "A number of cyclic and BCH code decoders that have 0(1) time complexity and less hardware complexity than conventional digital decoders are presented. The neural decoder is formulated as a set of parity networks in the first layer followed by a linear perceptron in the second layer, and thus has simple implementation in VLSI technology.",

author = "Tseng, {Yuen Hsien} and Wu, {Ja Ling}",

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AB - A number of cyclic and BCH code decoders that have 0(1) time complexity and less hardware complexity than conventional digital decoders are presented. The neural decoder is formulated as a set of parity networks in the first layer followed by a linear perceptron in the second layer, and thus has simple implementation in VLSI technology.

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Fast neural decoders for some cyclic codes

Abstract

ASJC Scopus subject areas

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