Fast neural decoders for some cyclic codes

Yuen Hsien Tseng, Ja Ling Wu

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


A number of cyclic and BCH code decoders that have 0(1) time complexity and less hardware complexity than conventional digital decoders are presented. The neural decoder is formulated as a set of parity networks in the first layer followed by a linear perceptron in the second layer, and thus has simple implementation in VLSI technology.

Original languageEnglish
Pages (from-to)595-600
Number of pages6
JournalInternational Journal of Electronics
Issue number4
Publication statusPublished - 1993 Oct
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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