Fast neural decoders for some cyclic codes

Yuen-Hsien Tseng, Ja Ling Wu

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A number of cyclic and BCH code decoders that have 0(1) time complexity and less hardware complexity than conventional digital decoders are presented. The neural decoder is formulated as a set of parity networks in the first layer followed by a linear perceptron in the second layer, and thus has simple implementation in VLSI technology.

Original languageEnglish
Pages (from-to)595-600
Number of pages6
JournalInternational Journal of Electronics
Volume75
Issue number4
DOIs
Publication statusPublished - 1993 Jan 1

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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