Fast knn classification based on softcore cpu and reconfigurable hardware

Hui Ya Li, Yao Jung Yeh, Wen Jyi Hwang

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


This paper presents a novel architecture for k-nearest neighbor (kNN) classification using field programmable gate array (FPGA). In the architecture, the first k closest vectors in the design set of a kNN classifier for each input vector are first identified by perfomung the partial distance search (PDS) in the wavelet domain. To implement the PDS in hardware, subspace search, bitplane reduction, multiple-coefficient accumulation and multiple-module computation techniques are employed for the effective reduction of the area complexity and computation latency. The proposed implementation has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the implementation provides acosteffective solution to the FPGA realization of kNN classification systems where both high throughput and low area cost are desired.

Original languageEnglish
Pages (from-to)431-446
Number of pages16
JournalIntelligent Automation and Soft Computing
Issue number4
Publication statusPublished - 2011 Jan


  • FPGA
  • Knn
  • Partial distance search
  • Reconfigurable computing

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Computational Theory and Mathematics
  • Artificial Intelligence


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