Fabrication and electron transport in vertical silicon-silicon nitride-silicon multilayer nano-pillars

Shu Fen Hu, Hsien Hsun Yang, Heng Tien Lin, Chin Lung Sung, Yue Min Wan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We have designed vertical single-electron transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. A part of surrounding gate arranges source, gate and drain vertically. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. The part surrounding gate transistor has a large effective channel width because the pillar silicon island is so small (< 10 nm) that can be used as a current channel region. Coulomb gap, Coulomb staircases and periodic current oscillation are observed at 300 K. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.

Original languageEnglish
Title of host publication2005 5th IEEE Conference on Nanotechnology
Pages745-748
Number of pages4
DOIs
Publication statusPublished - 2005 Dec 1
Event2005 5th IEEE Conference on Nanotechnology - Nagoya, Japan
Duration: 2005 Jul 112005 Jul 15

Publication series

Name2005 5th IEEE Conference on Nanotechnology
Volume2

Other

Other2005 5th IEEE Conference on Nanotechnology
CountryJapan
CityNagoya
Period05/7/1105/7/15

Fingerprint

Silicon nitride
Multilayers
Fabrication
Silicon
Transistors
Single electron transistors
Semiconductor quantum wells
Capacitance
Electrodes
Electron Transport

Keywords

  • Coulomb blockade
  • Nanoelectronics
  • Oscillation
  • Pillar

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Hu, S. F., Yang, H. H., Lin, H. T., Sung, C. L., & Wan, Y. M. (2005). Fabrication and electron transport in vertical silicon-silicon nitride-silicon multilayer nano-pillars. In 2005 5th IEEE Conference on Nanotechnology (pp. 745-748). [1500825] (2005 5th IEEE Conference on Nanotechnology; Vol. 2). https://doi.org/10.1109/NANO.2005.1500825

Fabrication and electron transport in vertical silicon-silicon nitride-silicon multilayer nano-pillars. / Hu, Shu Fen; Yang, Hsien Hsun; Lin, Heng Tien; Sung, Chin Lung; Wan, Yue Min.

2005 5th IEEE Conference on Nanotechnology. 2005. p. 745-748 1500825 (2005 5th IEEE Conference on Nanotechnology; Vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hu, SF, Yang, HH, Lin, HT, Sung, CL & Wan, YM 2005, Fabrication and electron transport in vertical silicon-silicon nitride-silicon multilayer nano-pillars. in 2005 5th IEEE Conference on Nanotechnology., 1500825, 2005 5th IEEE Conference on Nanotechnology, vol. 2, pp. 745-748, 2005 5th IEEE Conference on Nanotechnology, Nagoya, Japan, 05/7/11. https://doi.org/10.1109/NANO.2005.1500825
Hu SF, Yang HH, Lin HT, Sung CL, Wan YM. Fabrication and electron transport in vertical silicon-silicon nitride-silicon multilayer nano-pillars. In 2005 5th IEEE Conference on Nanotechnology. 2005. p. 745-748. 1500825. (2005 5th IEEE Conference on Nanotechnology). https://doi.org/10.1109/NANO.2005.1500825
Hu, Shu Fen ; Yang, Hsien Hsun ; Lin, Heng Tien ; Sung, Chin Lung ; Wan, Yue Min. / Fabrication and electron transport in vertical silicon-silicon nitride-silicon multilayer nano-pillars. 2005 5th IEEE Conference on Nanotechnology. 2005. pp. 745-748 (2005 5th IEEE Conference on Nanotechnology).
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