We have designed vertical single-electron transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. A part of surrounding gate arranges source, gate and drain vertically. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. The part surrounding gate transistor has a large effective channel width because the pillar silicon island is so small (< 10 nm) that can be used as a current channel region. Coulomb gap, Coulomb staircases and periodic current oscillation are observed at 300 K. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.