ESD protection for the tolerant I/O circuits using PESD implantation

Howard T.H. Tang; S. S. Chen; Scott Liu; M. T. Lee; C. H. Liu; M. C. Wang; M. C. Jeng

doi:10.1016/S0304-3886(01)00157-7

ESD protection for the tolerant I/O circuits using PESD implantation

Howard T.H. Tang^*, S. S. Chen, Scott Liu, M. T. Lee, C. H. Liu, M. C. Wang, M. C. Jeng

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

16 Citations (Scopus)

Abstract

In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call "PESD" implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μ process, this method provides a significant improvement in the cascode ESD performance.

Original language	English
Pages (from-to)	293-300
Number of pages	8
Journal	Journal of Electrostatics
Volume	54
Issue number	3-4
DOIs	https://doi.org/10.1016/S0304-3886(01)00157-7
Publication status	Published - 2002 Mar
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Biotechnology
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

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10.1016/S0304-3886(01)00157-7

Cite this

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title = "ESD protection for the tolerant I/O circuits using PESD implantation",

abstract = "In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call {"}PESD{"} implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μ process, this method provides a significant improvement in the cascode ESD performance.",

author = "Tang, {Howard T.H.} and Chen, {S. S.} and Scott Liu and Lee, {M. T.} and Liu, {C. H.} and Wang, {M. C.} and Jeng, {M. C.}",

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language = "English",

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journal = "Journal of Electrostatics",

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TY - JOUR

T1 - ESD protection for the tolerant I/O circuits using PESD implantation

AU - Tang, Howard T.H.

AU - Chen, S. S.

AU - Liu, Scott

AU - Lee, M. T.

AU - Liu, C. H.

AU - Wang, M. C.

AU - Jeng, M. C.

PY - 2002/3

Y1 - 2002/3

N2 - In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call "PESD" implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μ process, this method provides a significant improvement in the cascode ESD performance.

AB - In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call "PESD" implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μ process, this method provides a significant improvement in the cascode ESD performance.

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EP - 300

JO - Journal of Electrostatics

JF - Journal of Electrostatics

IS - 3-4

ER -

ESD protection for the tolerant I/O circuits using PESD implantation

Abstract

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