ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications

Ming Dou Ker; Chun Yu Lin; Yi Han Wu; Wen Tai Wang

doi:10.1109/CYBER.2017.8446566

ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications

Ming Dou Ker, Chun Yu Lin, Yi Han Wu, Wen Tai Wang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

On-chip electrostatic discharge (ESD) protection design with low-leakage consideration for the silicon chips of IoT applications is presented. The proposed ESD protection design uses the fast turn-on silicon-controlled rectifier (SCR) device to implement the power-rail ESD clamp circuit. Experimental results verified in TSMC 28nm CMOS process have shown that the proposed design has advantages of low leakage current (2∼3nA), low trigger voltage (∼2V), high ESD robustness (>8kV), and free to latchup issue.

Original language	English
Title of host publication	2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1496-1499
Number of pages	4
ISBN (Print)	9781538604892
DOIs	https://doi.org/10.1109/CYBER.2017.8446566
Publication status	Published - 2018 Aug 24
Event	7th IEEE Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017 - Honolulu, United States Duration: 2017 Jul 31 → 2017 Aug 4

Publication series

Name	2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017

Conference

Conference	7th IEEE Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017
Country/Territory	United States
City	Honolulu
Period	2017/07/31 → 2017/08/04

Keywords

CMOS
ESD protection
electrostatic discharge (ESD)
low-leakage

ASJC Scopus subject areas

Artificial Intelligence
Computer Science Applications
Control and Optimization

Access to Document

10.1109/CYBER.2017.8446566

Cite this

Ker, M. D., Lin, C. Y., Wu, Y. H., & Wang, W. T. (2018). ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications. In 2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017 (pp. 1496-1499). Article 8446566 (2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CYBER.2017.8446566

ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications. / Ker, Ming Dou; Lin, Chun Yu; Wu, Yi Han et al.
2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1496-1499 8446566 (2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ker, MD, Lin, CY, Wu, YH & Wang, WT 2018, ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications. in 2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017., 8446566, 2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017, Institute of Electrical and Electronics Engineers Inc., pp. 1496-1499, 7th IEEE Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017, Honolulu, United States, 2017/07/31. https://doi.org/10.1109/CYBER.2017.8446566

Ker MD, Lin CY, Wu YH, Wang WT. ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications. In 2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1496-1499. 8446566. (2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017). doi: 10.1109/CYBER.2017.8446566

Ker, Ming Dou ; Lin, Chun Yu ; Wu, Yi Han et al. / ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications. 2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1496-1499 (2017 IEEE 7th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, CYBER 2017).

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abstract = "On-chip electrostatic discharge (ESD) protection design with low-leakage consideration for the silicon chips of IoT applications is presented. The proposed ESD protection design uses the fast turn-on silicon-controlled rectifier (SCR) device to implement the power-rail ESD clamp circuit. Experimental results verified in TSMC 28nm CMOS process have shown that the proposed design has advantages of low leakage current (2∼3nA), low trigger voltage (∼2V), high ESD robustness (>8kV), and free to latchup issue.",

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author = "Ker, {Ming Dou} and Lin, {Chun Yu} and Wu, {Yi Han} and Wang, {Wen Tai}",

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AU - Ker, Ming Dou

AU - Lin, Chun Yu

AU - Wu, Yi Han

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N2 - On-chip electrostatic discharge (ESD) protection design with low-leakage consideration for the silicon chips of IoT applications is presented. The proposed ESD protection design uses the fast turn-on silicon-controlled rectifier (SCR) device to implement the power-rail ESD clamp circuit. Experimental results verified in TSMC 28nm CMOS process have shown that the proposed design has advantages of low leakage current (2∼3nA), low trigger voltage (∼2V), high ESD robustness (>8kV), and free to latchup issue.

AB - On-chip electrostatic discharge (ESD) protection design with low-leakage consideration for the silicon chips of IoT applications is presented. The proposed ESD protection design uses the fast turn-on silicon-controlled rectifier (SCR) device to implement the power-rail ESD clamp circuit. Experimental results verified in TSMC 28nm CMOS process have shown that the proposed design has advantages of low leakage current (2∼3nA), low trigger voltage (∼2V), high ESD robustness (>8kV), and free to latchup issue.

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ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications

Abstract

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Keywords

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