ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology

Chun Yu Lin; Li Wei Chu; Shiang Yu Tsai; Ming Dou Ker; Ming Hsiang Song; Chewn Pu Jou; Tse Hua Lu; Jen Chou Tseng; Ming Hsien Tsai; Tsun Lai Hsu; Ping Fang Hung; Yu Lin Wei; Tzu Heng Chang

doi:10.1109/NANO.2013.6720810

ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology

Chun Yu Lin, Li Wei Chu, Shiang Yu Tsai, Ming Dou Ker, Ming Hsiang Song, Chewn Pu Jou, Tse Hua Lu, Jen Chou Tseng, Ming Hsien Tsai, Tsun Lai Hsu, Ping Fang Hung, Yu Lin Wei, Tzu Heng Chang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Nanoscale CMOS technologies have been used to implement the radio-frequency integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection on circuit performances, ESD protection at input/output pads must be carefully designed. In this work, a new proposed ESD protection design has been realized in a nanoscale CMOS process. Experimental results of the test circuits have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.

Original language	English
Title of host publication	2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013
Pages	241-244
Number of pages	4
DOIs	https://doi.org/10.1109/NANO.2013.6720810
Publication status	Published - 2013
Externally published	Yes
Event	2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013 - Beijing, China Duration: 2013 Aug 5 → 2013 Aug 8

Publication series

Name	Proceedings of the IEEE Conference on Nanotechnology
ISSN (Print)	1944-9399
ISSN (Electronic)	1944-9380

Other

Other	2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013
Country/Territory	China
City	Beijing
Period	2013/08/05 → 2013/08/08

ASJC Scopus subject areas

Bioengineering
Electrical and Electronic Engineering
Materials Chemistry
Condensed Matter Physics

Access to Document

10.1109/NANO.2013.6720810

Cite this

Lin, C. Y., Chu, L. W., Tsai, S. Y., Ker, M. D., Song, M. H., Jou, C. P., Lu, T. H., Tseng, J. C., Tsai, M. H., Hsu, T. L., Hung, P. F., Wei, Y. L., & Chang, T. H. (2013). ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology. In 2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013 (pp. 241-244). Article 6720810 (Proceedings of the IEEE Conference on Nanotechnology). https://doi.org/10.1109/NANO.2013.6720810

ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology. / Lin, Chun Yu; Chu, Li Wei; Tsai, Shiang Yu et al.
2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013. 2013. p. 241-244 6720810 (Proceedings of the IEEE Conference on Nanotechnology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, CY, Chu, LW, Tsai, SY, Ker, MD, Song, MH, Jou, CP, Lu, TH, Tseng, JC, Tsai, MH, Hsu, TL, Hung, PF, Wei, YL & Chang, TH 2013, ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology. in 2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013., 6720810, Proceedings of the IEEE Conference on Nanotechnology, pp. 241-244, 2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013, Beijing, China, 2013/08/05. https://doi.org/10.1109/NANO.2013.6720810

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title = "ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology",

abstract = "Nanoscale CMOS technologies have been used to implement the radio-frequency integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection on circuit performances, ESD protection at input/output pads must be carefully designed. In this work, a new proposed ESD protection design has been realized in a nanoscale CMOS process. Experimental results of the test circuits have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.",

author = "Lin, {Chun Yu} and Chu, {Li Wei} and Tsai, {Shiang Yu} and Ker, {Ming Dou} and Song, {Ming Hsiang} and Jou, {Chewn Pu} and Lu, {Tse Hua} and Tseng, {Jen Chou} and Tsai, {Ming Hsien} and Hsu, {Tsun Lai} and Hung, {Ping Fang} and Wei, {Yu Lin} and Chang, {Tzu Heng}",

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AU - Song, Ming Hsiang

AU - Jou, Chewn Pu

AU - Lu, Tse Hua

AU - Tseng, Jen Chou

AU - Tsai, Ming Hsien

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AU - Hung, Ping Fang

AU - Wei, Yu Lin

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AB - Nanoscale CMOS technologies have been used to implement the radio-frequency integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection on circuit performances, ESD protection at input/output pads must be carefully designed. In this work, a new proposed ESD protection design has been realized in a nanoscale CMOS process. Experimental results of the test circuits have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.

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ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology

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