ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology

Chun Yu Lin, Li Wei Chu, Shiang Yu Tsai, Ming Dou Ker, Ming Hsiang Song, Chewn Pu Jou, Tse Hua Lu, Jen Chou Tseng, Ming Hsien Tsai, Tsun Lai Hsu, Ping Fang Hung, Yu Lin Wei, Tzu Heng Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Nanoscale CMOS technologies have been used to implement the radio-frequency integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection on circuit performances, ESD protection at input/output pads must be carefully designed. In this work, a new proposed ESD protection design has been realized in a nanoscale CMOS process. Experimental results of the test circuits have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.

Original languageEnglish
Title of host publication2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013
Pages241-244
Number of pages4
DOIs
Publication statusPublished - 2013 Dec 1
Event2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013 - Beijing, China
Duration: 2013 Aug 52013 Aug 8

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Other

Other2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013
CountryChina
CityBeijing
Period13/8/513/8/8

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ASJC Scopus subject areas

  • Bioengineering
  • Electrical and Electronic Engineering
  • Materials Chemistry
  • Condensed Matter Physics

Cite this

Lin, C. Y., Chu, L. W., Tsai, S. Y., Ker, M. D., Song, M. H., Jou, C. P., Lu, T. H., Tseng, J. C., Tsai, M. H., Hsu, T. L., Hung, P. F., Wei, Y. L., & Chang, T. H. (2013). ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology. In 2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013 (pp. 241-244). [6720810] (Proceedings of the IEEE Conference on Nanotechnology). https://doi.org/10.1109/NANO.2013.6720810