ESD protection design for high-speed circuits in nanoscale CMOS process

Chun Yu Lin; Rong Kun Chang

doi:10.1109/ISICIR.2016.7829726

ESD protection design for high-speed circuits in nanoscale CMOS process

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

To protect the high-speed integrated circuits from electrostatic discharge (ESD) damages, the ESD protection design of inductor-assisted silicon-controlled rectifier (LASCR) is investigated in this work. Compared with the conventional ESD protection design of dual-diode, the LASCR has better high-speed performances and higher ESD robustness. Therefore, the LASCR is very suitable for high-speed applications.

Original language	English
Title of host publication	2016 International Symposium on Integrated Circuits, ISIC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467390194
DOIs	https://doi.org/10.1109/ISICIR.2016.7829726
Publication status	Published - 2017 Jan 23
Event	2016 International Symposium on Integrated Circuits, ISIC 2016 - Singapore, Singapore Duration: 2016 Dec 12 → 2016 Dec 14

Publication series

Name	2016 International Symposium on Integrated Circuits, ISIC 2016

Conference

Conference	2016 International Symposium on Integrated Circuits, ISIC 2016
Country	Singapore
City	Singapore
Period	16/12/12 → 16/12/14

Keywords

CMOS
electrostatic discharge (ESD) protection
high-speed circuits

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Computer Networks and Communications
Hardware and Architecture

Access to Document

10.1109/ISICIR.2016.7829726

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Cite this

Lin, C. Y., & Chang, R. K. (2017). ESD protection design for high-speed circuits in nanoscale CMOS process. In 2016 International Symposium on Integrated Circuits, ISIC 2016 [7829726] (2016 International Symposium on Integrated Circuits, ISIC 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISICIR.2016.7829726

ESD protection design for high-speed circuits in nanoscale CMOS process. / Lin, Chun Yu; Chang, Rong Kun.

2016 International Symposium on Integrated Circuits, ISIC 2016. Institute of Electrical and Electronics Engineers Inc., 2017. 7829726 (2016 International Symposium on Integrated Circuits, ISIC 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, CY & Chang, RK 2017, ESD protection design for high-speed circuits in nanoscale CMOS process. in 2016 International Symposium on Integrated Circuits, ISIC 2016., 7829726, 2016 International Symposium on Integrated Circuits, ISIC 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on Integrated Circuits, ISIC 2016, Singapore, Singapore, 16/12/12. https://doi.org/10.1109/ISICIR.2016.7829726

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