ESD protection design for high-speed circuits in nanoscale CMOS process

Chun Yu Lin, Rong Kun Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

To protect the high-speed integrated circuits from electrostatic discharge (ESD) damages, the ESD protection design of inductor-assisted silicon-controlled rectifier (LASCR) is investigated in this work. Compared with the conventional ESD protection design of dual-diode, the LASCR has better high-speed performances and higher ESD robustness. Therefore, the LASCR is very suitable for high-speed applications.

Original languageEnglish
Title of host publication2016 International Symposium on Integrated Circuits, ISIC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467390194
DOIs
Publication statusPublished - 2017 Jan 23
Event2016 International Symposium on Integrated Circuits, ISIC 2016 - Singapore, Singapore
Duration: 2016 Dec 122016 Dec 14

Publication series

Name2016 International Symposium on Integrated Circuits, ISIC 2016

Conference

Conference2016 International Symposium on Integrated Circuits, ISIC 2016
CountrySingapore
CitySingapore
Period16/12/1216/12/14

Fingerprint

Electrostatic discharge
Networks (circuits)
Thyristors
Integrated circuits
Diodes

Keywords

  • CMOS
  • electrostatic discharge (ESD) protection
  • high-speed circuits

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Lin, C. Y., & Chang, R. K. (2017). ESD protection design for high-speed circuits in nanoscale CMOS process. In 2016 International Symposium on Integrated Circuits, ISIC 2016 [7829726] (2016 International Symposium on Integrated Circuits, ISIC 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISICIR.2016.7829726

ESD protection design for high-speed circuits in nanoscale CMOS process. / Lin, Chun Yu; Chang, Rong Kun.

2016 International Symposium on Integrated Circuits, ISIC 2016. Institute of Electrical and Electronics Engineers Inc., 2017. 7829726 (2016 International Symposium on Integrated Circuits, ISIC 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lin, CY & Chang, RK 2017, ESD protection design for high-speed circuits in nanoscale CMOS process. in 2016 International Symposium on Integrated Circuits, ISIC 2016., 7829726, 2016 International Symposium on Integrated Circuits, ISIC 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on Integrated Circuits, ISIC 2016, Singapore, Singapore, 16/12/12. https://doi.org/10.1109/ISICIR.2016.7829726
Lin CY, Chang RK. ESD protection design for high-speed circuits in nanoscale CMOS process. In 2016 International Symposium on Integrated Circuits, ISIC 2016. Institute of Electrical and Electronics Engineers Inc. 2017. 7829726. (2016 International Symposium on Integrated Circuits, ISIC 2016). https://doi.org/10.1109/ISICIR.2016.7829726
Lin, Chun Yu ; Chang, Rong Kun. / ESD protection design for high-speed circuits in nanoscale CMOS process. 2016 International Symposium on Integrated Circuits, ISIC 2016. Institute of Electrical and Electronics Engineers Inc., 2017. (2016 International Symposium on Integrated Circuits, ISIC 2016).
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