ESD protection design for high-speed applications in CMOS technology

Jie Ting Chen, Chun Yu Lin, Rong Kun Chang, Ming Dou Ker, Tzu Chien Tzeng, Tzu Chiang Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded siliconcontrolled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.

Original languageEnglish
Title of host publication2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509009169
DOIs
Publication statusPublished - 2016 Jul 2
Event59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016 - Abu Dhabi, United Arab Emirates
Duration: 2016 Oct 162016 Oct 19

Publication series

NameMidwest Symposium on Circuits and Systems
Volume0
ISSN (Print)1548-3746

Other

Other59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016
CountryUnited Arab Emirates
CityAbu Dhabi
Period16/10/1616/10/19

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Chen, J. T., Lin, C. Y., Chang, R. K., Ker, M. D., Tzeng, T. C., & Lin, T. C. (2016). ESD protection design for high-speed applications in CMOS technology. In 2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016 [7870016] (Midwest Symposium on Circuits and Systems; Vol. 0). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2016.7870016