ESD protection design for gigahertz differential LNA in a 65-nm CMOS process

Chun Yu Lin; Mei Lian Fan; Wei Hao Fu

doi:10.1109/APEMC.2015.7175245

ESD protection design for gigahertz differential LNA in a 65-nm CMOS process

Chun Yu Lin, Mei Lian Fan, Wei Hao Fu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The electrostatic discharge (ESD) immunity test for EMC was one important reliability regulation. The turn-on-efficient on-chip ESD protection circuit is required to clamp the overstress voltage. A new design of ESD protection diodes with embedded silicon-controlled rectifier (SCR) was proposed to protect the gigahertz differential low-noise amplifier (LNA). Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.

Original language	English
Title of host publication	2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	322-324
Number of pages	3
ISBN (Electronic)	9781479966707
DOIs	https://doi.org/10.1109/APEMC.2015.7175245
Publication status	Published - 2015 Aug 3
Event	Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015 - Taipei, Taiwan Duration: 2015 May 25 → 2015 May 29

Publication series

Name	2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015

Other

Other	Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015
Country/Territory	Taiwan
City	Taipei
Period	2015/05/25 → 2015/05/29

ASJC Scopus subject areas

Electrical and Electronic Engineering
Radiation

Access to Document

10.1109/APEMC.2015.7175245

Cite this

Lin, C. Y., Fan, M. L., & Fu, W. H. (2015). ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. In 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015 (pp. 322-324). Article 7175245 (2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APEMC.2015.7175245

ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. / Lin, Chun Yu; Fan, Mei Lian; Fu, Wei Hao.
2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 322-324 7175245 (2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, CY, Fan, ML & Fu, WH 2015, ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. in 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015., 7175245, 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 322-324, Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015, Taipei, Taiwan, 2015/05/25. https://doi.org/10.1109/APEMC.2015.7175245

Lin CY, Fan ML, Fu WH. ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. In 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 322-324. 7175245. (2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015). doi: 10.1109/APEMC.2015.7175245

Lin, Chun Yu ; Fan, Mei Lian ; Fu, Wei Hao. / ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 322-324 (2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015).

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ESD protection design for gigahertz differential LNA in a 65-nm CMOS process

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