ESD protection design for gigahertz differential LNA in a 65-nm CMOS process

Chun-Yu Lin, Mei Lian Fan, Wei Hao Fu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The electrostatic discharge (ESD) immunity test for EMC was one important reliability regulation. The turn-on-efficient on-chip ESD protection circuit is required to clamp the overstress voltage. A new design of ESD protection diodes with embedded silicon-controlled rectifier (SCR) was proposed to protect the gigahertz differential low-noise amplifier (LNA). Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.

Original languageEnglish
Title of host publication2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages322-324
Number of pages3
ISBN (Electronic)9781479966707
DOIs
Publication statusPublished - 2015 Aug 3
EventAsia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015 - Taipei, Taiwan
Duration: 2015 May 252015 May 29

Other

OtherAsia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015
CountryTaiwan
CityTaipei
Period15/5/2515/5/29

Fingerprint

Differential amplifiers
Electrostatic discharge
Low noise amplifiers
low noise
CMOS
amplifiers
electrostatics
circuit protection
silicon controlled rectifiers
clamps
Clamping devices
immunity
Electromagnetic compatibility
Thyristors
Diodes
diodes
chips
Networks (circuits)
Electric potential
electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Radiation

Cite this

Lin, C-Y., Fan, M. L., & Fu, W. H. (2015). ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. In 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015 (pp. 322-324). [7175245] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APEMC.2015.7175245

ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. / Lin, Chun-Yu; Fan, Mei Lian; Fu, Wei Hao.

2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 322-324 7175245.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lin, C-Y, Fan, ML & Fu, WH 2015, ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. in 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015., 7175245, Institute of Electrical and Electronics Engineers Inc., pp. 322-324, Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015, Taipei, Taiwan, 15/5/25. https://doi.org/10.1109/APEMC.2015.7175245
Lin C-Y, Fan ML, Fu WH. ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. In 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 322-324. 7175245 https://doi.org/10.1109/APEMC.2015.7175245
Lin, Chun-Yu ; Fan, Mei Lian ; Fu, Wei Hao. / ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 322-324
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