ESD protection consideration in nanoscale CMOS technology

Ming Dou Ker, Chun Yu Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

The thinner gate oxide in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of IC products. As the feature sizes in nanoscale CMOS technologies are further scaling down, the on-chip ESD protection designs are more challenging. The ESD protection considerations, including ESD design window, area efficiency, leakage current, and high-voltage tolerance, were presented in this abstract. Some possible solutions against these issues in nanoscale CMOS technologies were also included in this paper.

Original languageEnglish
Title of host publication2011 11th IEEE International Conference on Nanotechnology, NANO 2011
Pages720-723
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 11th IEEE International Conference on Nanotechnology, NANO 2011 - Portland, OR, United States
Duration: 2011 Aug 152011 Aug 19

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Other

Other2011 11th IEEE International Conference on Nanotechnology, NANO 2011
CountryUnited States
CityPortland, OR
Period11/8/1511/8/19

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Keywords

  • CMOS
  • electrostatic discharge (ESD)
  • on-chip ESD protection

ASJC Scopus subject areas

  • Bioengineering
  • Electrical and Electronic Engineering
  • Materials Chemistry
  • Condensed Matter Physics

Cite this

Ker, M. D., & Lin, C. Y. (2011). ESD protection consideration in nanoscale CMOS technology. In 2011 11th IEEE International Conference on Nanotechnology, NANO 2011 (pp. 720-723). [6144345] (Proceedings of the IEEE Conference on Nanotechnology). https://doi.org/10.1109/NANO.2011.6144345