Embedded a low area 32-bit AES for image encryption/decryption application

Kuo Huang Chang, Yi Cheng Chen, Chung Cheng Hsieh, Chi Wu Huang, Chi Jeng Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages1922-1925
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
Duration: 2009 May 242009 May 27

Other

Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CountryTaiwan
CityTaipei
Period09/5/2409/5/27

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Chang, K. H., Chen, Y. C., Hsieh, C. C., Huang, C. W., & Chang, C. J. (2009). Embedded a low area 32-bit AES for image encryption/decryption application. In 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 (pp. 1922-1925). [5118159] https://doi.org/10.1109/ISCAS.2009.5118159