Abstract
Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.
| Original language | English |
|---|---|
| Title of host publication | 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 |
| Pages | 1922-1925 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2009 |
| Event | 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan Duration: 2009 May 24 → 2009 May 27 |
Other
| Other | 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 |
|---|---|
| Country | Taiwan |
| City | Taipei |
| Period | 09/5/24 → 09/5/27 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Embedded a low area 32-bit AES for image encryption/decryption application. / Chang, Kuo Huang; Chen, Yi Cheng; Hsieh, Chung Cheng; Huang, Chi Wu; Chang, Chi Jeng.
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. 2009. p. 1922-1925 5118159.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Embedded a low area 32-bit AES for image encryption/decryption application
AU - Chang, Kuo Huang
AU - Chen, Yi Cheng
AU - Hsieh, Chung Cheng
AU - Huang, Chi Wu
AU - Chang, Chi Jeng
PY - 2009
Y1 - 2009
N2 - Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.
AB - Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.
UR - http://www.scopus.com/inward/record.url?scp=70350154494&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70350154494&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2009.5118159
DO - 10.1109/ISCAS.2009.5118159
M3 - Conference contribution
AN - SCOPUS:70350154494
SN - 9781424438280
SP - 1922
EP - 1925
BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
ER -