Embedded a low area 32-bit AES for image encryption/decryption application

Kuo Huang Chang; Yi Cheng Chen; Chung Cheng Hsieh; Chi Wu Huang; Chi Jeng Chang

doi:10.1109/ISCAS.2009.5118159

Embedded a low area 32-bit AES for image encryption/decryption application

Kuo Huang Chang, Yi Cheng Chen, Chung Cheng Hsieh, Chi Wu Huang, Chi Jeng Chang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

Original language	English
Title of host publication	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages	1922-1925
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2009.5118159
Publication status	Published - 2009
Event	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan Duration: 2009 May 24 → 2009 May 27

Other

Other	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/Territory	Taiwan
City	Taipei
Period	2009/05/24 → 2009/05/27

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2009.5118159

Cite this

Chang, KH, Chen, YC, Hsieh, CC, Huang, CW & Chang, CJ 2009, Embedded a low area 32-bit AES for image encryption/decryption application. in 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5118159, pp. 1922-1925, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, 2009/05/24. https://doi.org/10.1109/ISCAS.2009.5118159

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abstract = "Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.",

author = "Chang, {Kuo Huang} and Chen, {Yi Cheng} and Hsieh, {Chung Cheng} and Huang, {Chi Wu} and Chang, {Chi Jeng}",

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AB - Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

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Embedded a low area 32-bit AES for image encryption/decryption application

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