Embedded a low area 32-bit AES for image encryption/decryption application

Kuo Huang Chang, Yi Cheng Chen, Chung Cheng Hsieh, Chi Wu Huang, Chi Jeng Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages1922-1925
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
Duration: 2009 May 242009 May 27

Other

Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CountryTaiwan
CityTaipei
Period09/5/2409/5/27

Fingerprint

Cryptography
Field programmable gate arrays (FPGA)
Throughput
Application specific integrated circuits
Computer hardware
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Chang, K. H., Chen, Y. C., Hsieh, C. C., Huang, C. W., & Chang, C. J. (2009). Embedded a low area 32-bit AES for image encryption/decryption application. In 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 (pp. 1922-1925). [5118159] https://doi.org/10.1109/ISCAS.2009.5118159

Embedded a low area 32-bit AES for image encryption/decryption application. / Chang, Kuo Huang; Chen, Yi Cheng; Hsieh, Chung Cheng; Huang, Chi Wu; Chang, Chi Jeng.

2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. 2009. p. 1922-1925 5118159.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chang, KH, Chen, YC, Hsieh, CC, Huang, CW & Chang, CJ 2009, Embedded a low area 32-bit AES for image encryption/decryption application. in 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5118159, pp. 1922-1925, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, 09/5/24. https://doi.org/10.1109/ISCAS.2009.5118159
Chang KH, Chen YC, Hsieh CC, Huang CW, Chang CJ. Embedded a low area 32-bit AES for image encryption/decryption application. In 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. 2009. p. 1922-1925. 5118159 https://doi.org/10.1109/ISCAS.2009.5118159
Chang, Kuo Huang ; Chen, Yi Cheng ; Hsieh, Chung Cheng ; Huang, Chi Wu ; Chang, Chi Jeng. / Embedded a low area 32-bit AES for image encryption/decryption application. 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. 2009. pp. 1922-1925
@inproceedings{8c452c66f4de499391d7ecd4ff0c384f,
title = "Embedded a low area 32-bit AES for image encryption/decryption application",
abstract = "Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.",
author = "Chang, {Kuo Huang} and Chen, {Yi Cheng} and Hsieh, {Chung Cheng} and Huang, {Chi Wu} and Chang, {Chi Jeng}",
year = "2009",
doi = "10.1109/ISCAS.2009.5118159",
language = "English",
isbn = "9781424438280",
pages = "1922--1925",
booktitle = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009",

}

TY - GEN

T1 - Embedded a low area 32-bit AES for image encryption/decryption application

AU - Chang, Kuo Huang

AU - Chen, Yi Cheng

AU - Hsieh, Chung Cheng

AU - Huang, Chi Wu

AU - Chang, Chi Jeng

PY - 2009

Y1 - 2009

N2 - Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

AB - Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

UR - http://www.scopus.com/inward/record.url?scp=70350154494&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70350154494&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2009.5118159

DO - 10.1109/ISCAS.2009.5118159

M3 - Conference contribution

AN - SCOPUS:70350154494

SN - 9781424438280

SP - 1922

EP - 1925

BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

ER -