Efficient VLSI architecture for training radial basis function networks

Zhe Cheng Fan, Wen Jyi Hwang

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

Original languageEnglish
Pages (from-to)3848-3877
Number of pages30
JournalSensors (Switzerland)
Volume13
Issue number3
DOIs
Publication statusPublished - 2013 Mar

Fingerprint

Radial basis function networks
very large scale integration
Least-Squares Analysis
education
Networks (circuits)
Weights and Measures
Particle accelerators
Field programmable gate arrays (FPGA)
field-programmable gate arrays
Hardware
hardware
accelerators
chips
output

Keywords

  • FPGA
  • Fuzzy C-means
  • Radial basis function
  • Reconfigurable computing
  • System on programmable chip

ASJC Scopus subject areas

  • Analytical Chemistry
  • Atomic and Molecular Physics, and Optics
  • Biochemistry
  • Electrical and Electronic Engineering

Cite this

Efficient VLSI architecture for training radial basis function networks. / Fan, Zhe Cheng; Hwang, Wen Jyi.

In: Sensors (Switzerland), Vol. 13, No. 3, 03.2013, p. 3848-3877.

Research output: Contribution to journalArticle

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