Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm

Wen Jyi Hwang; Hao Chen

Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm

Wen Jyi Hwang, Hao Chen

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A novel hardware architecture for fast spike sorting is presented in this paper. The architecture is able to perform feature extraction based on the Generalized Hebbian Algorithm (GHA). The employment of GHA allows efficient computation of principal components for subsequent clustering and classification operations. The hardware implementations of GHA features high throughput and low area costs. The proposed architecture is implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip(SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining low hardware resource utilization and high speed computation.

Original language	English
Title of host publication	ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning
Pages	71-76
Number of pages	6
Publication status	Published - 2013
Event	21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2013 - Bruges, Belgium Duration: 2013 Apr 24 → 2013 Apr 26

Publication series

Name	ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning

Other

Other	21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2013
Country/Territory	Belgium
City	Bruges
Period	2013/04/24 → 2013/04/26

ASJC Scopus subject areas

Artificial Intelligence
Information Systems

Cite this

Hwang, W. J., & Chen, H. (2013). Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm. In ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning (pp. 71-76). (ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning).

Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm. / Hwang, Wen Jyi; Chen, Hao.
ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning. 2013. p. 71-76 (ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hwang, WJ & Chen, H 2013, Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm. in ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning. ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, pp. 71-76, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2013, Bruges, Belgium, 2013/04/24.

Hwang WJ, Chen H. Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm. In ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning. 2013. p. 71-76. (ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning).

Hwang, Wen Jyi ; Chen, Hao. / Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm. ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning. 2013. pp. 71-76 (ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning).

@inproceedings{c1e8d7fae5cf4948b381f7938d9d6386,

title = "Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm",

abstract = "A novel hardware architecture for fast spike sorting is presented in this paper. The architecture is able to perform feature extraction based on the Generalized Hebbian Algorithm (GHA). The employment of GHA allows efficient computation of principal components for subsequent clustering and classification operations. The hardware implementations of GHA features high throughput and low area costs. The proposed architecture is implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip(SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining low hardware resource utilization and high speed computation.",

author = "Hwang, {Wen Jyi} and Hao Chen",

year = "2013",

language = "English",

isbn = "9782874190810",

series = "ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning",

pages = "71--76",

booktitle = "ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning",

note = "21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2013 ; Conference date: 24-04-2013 Through 26-04-2013",

}

TY - GEN

T1 - Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm

AU - Hwang, Wen Jyi

AU - Chen, Hao

PY - 2013

Y1 - 2013

N2 - A novel hardware architecture for fast spike sorting is presented in this paper. The architecture is able to perform feature extraction based on the Generalized Hebbian Algorithm (GHA). The employment of GHA allows efficient computation of principal components for subsequent clustering and classification operations. The hardware implementations of GHA features high throughput and low area costs. The proposed architecture is implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip(SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining low hardware resource utilization and high speed computation.

AB - A novel hardware architecture for fast spike sorting is presented in this paper. The architecture is able to perform feature extraction based on the Generalized Hebbian Algorithm (GHA). The employment of GHA allows efficient computation of principal components for subsequent clustering and classification operations. The hardware implementations of GHA features high throughput and low area costs. The proposed architecture is implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip(SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining low hardware resource utilization and high speed computation.

UR - http://www.scopus.com/inward/record.url?scp=84887093873&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84887093873&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84887093873

SN - 9782874190810

T3 - ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning

SP - 71

EP - 76

BT - ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning

T2 - 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2013

Y2 - 24 April 2013 through 26 April 2013

ER -

Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm

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