Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm

Wen-Jyi Hwang, Hao Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A novel hardware architecture for fast spike sorting is presented in this paper. The architecture is able to perform feature extraction based on the Generalized Hebbian Algorithm (GHA). The employment of GHA allows efficient computation of principal components for subsequent clustering and classification operations. The hardware implementations of GHA features high throughput and low area costs. The proposed architecture is implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip(SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining low hardware resource utilization and high speed computation.

Original languageEnglish
Title of host publicationESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning
Pages71-76
Number of pages6
Publication statusPublished - 2013 Nov 11
Event21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2013 - Bruges, Belgium
Duration: 2013 Apr 242013 Apr 26

Publication series

NameESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning

Other

Other21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2013
CountryBelgium
CityBruges
Period13/4/2413/4/26

Fingerprint

Sorting
Hardware
Field programmable gate arrays (FPGA)
Feature extraction
Throughput
Costs

ASJC Scopus subject areas

  • Artificial Intelligence
  • Information Systems

Cite this

Hwang, W-J., & Chen, H. (2013). Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm. In ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning (pp. 71-76). (ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning).

Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm. / Hwang, Wen-Jyi; Chen, Hao.

ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning. 2013. p. 71-76 (ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hwang, W-J & Chen, H 2013, Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm. in ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning. ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, pp. 71-76, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2013, Bruges, Belgium, 13/4/24.
Hwang W-J, Chen H. Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm. In ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning. 2013. p. 71-76. (ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning).
Hwang, Wen-Jyi ; Chen, Hao. / Efficient VLSI architecture for spike sorting based on generalized Hebbian algorithm. ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning. 2013. pp. 71-76 (ESANN 2013 proceedings, 21st European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning).
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