Efficient pipelined architecture for competitive learning

Hui Ya Li, Chia Lung Hung, Wen Jyi Hwang*, Yi Tsan Hung

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


This paper presents a novel pipelined architecture for competitive learning (CL). The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for reducing the computation time. In the architecture, a novel codeword swapping scheme is adopted so that neuron competitions for different training vectors can be operated concurrently. The neuron updating process is based on a hardware divider with simple table lookup operations. The divider performs finite precision calculations for area cost reduction at the expense of slight degradation in training performance. The CPU time of the NIOS processor executing the CL training with the proposed architecture as an accelerator is measured. Experimental results show that the NIOS processor with the proposed architecture as an accelerator can achieve up to a speedup of 254 over its software counterpart running on a general purpose processor Pentium IV without hardware support.

Original languageEnglish
Pages (from-to)236-244
Number of pages9
JournalJournal of Parallel and Distributed Computing
Issue number2
Publication statusPublished - 2011 Feb


  • Clustering analysis
  • Competitive learning
  • FPGA
  • Reconfigurable computing
  • System on programmable chip
  • WTA

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence


Dive into the research topics of 'Efficient pipelined architecture for competitive learning'. Together they form a unique fingerprint.

Cite this