Efficient phase unwrapping architecture for digital holographic microscopy

Wen Jyi Hwang*, Shih Chang Cheng, Chau Jern Cheng

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize throughput of the computation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system.

Original languageEnglish
Pages (from-to)9160-9181
Number of pages22
Issue number10
Publication statusPublished - 2011 Oct


  • Digital holographic microscopy
  • FPGA
  • Phase unwrapping
  • Reconfigurable computing
  • System on programmable chip

ASJC Scopus subject areas

  • Analytical Chemistry
  • Biochemistry
  • Atomic and Molecular Physics, and Optics
  • Instrumentation
  • Electrical and Electronic Engineering


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