Efficient memetic vector quantizer design based on reconfigurable hardware and softcore processor

Wen-Jyi Hwang, Sheng Kai Weng, Ting Kuan Lin

Research output: Contribution to journalArticle

Abstract

This paper presents a novel hardware architecture for memetic vector quantizer (VQ) design. The architecture uses steady-state genetic algorithm (GA) for global search, and C-Means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state CA operations. It also uses a pipeline architecture for the hardware implementation of C-Means algorithm. The proposed architecture is embedded in a softcore CPU, and implemented on a field programmable logic array (FPGA) device for physical performance measurement. Experimental results show that the proposed architecture is an effective method for VQ optimization attaining both high performance and low computational time.

Original languageEnglish
Pages (from-to)905-914
Number of pages10
JournalJournal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an
Volume32
Issue number7
DOIs
Publication statusPublished - 2009 Jan 1

Fingerprint

Reconfigurable hardware
Hardware
Shift registers
Program processors
Pipelines
Genetic algorithms
Networks (circuits)

Keywords

  • Embedded hardware
  • Memetic algorithm
  • Reconfigurable computing
  • Vector quantization

ASJC Scopus subject areas

  • Engineering(all)

Cite this

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abstract = "This paper presents a novel hardware architecture for memetic vector quantizer (VQ) design. The architecture uses steady-state genetic algorithm (GA) for global search, and C-Means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state CA operations. It also uses a pipeline architecture for the hardware implementation of C-Means algorithm. The proposed architecture is embedded in a softcore CPU, and implemented on a field programmable logic array (FPGA) device for physical performance measurement. Experimental results show that the proposed architecture is an effective method for VQ optimization attaining both high performance and low computational time.",
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AB - This paper presents a novel hardware architecture for memetic vector quantizer (VQ) design. The architecture uses steady-state genetic algorithm (GA) for global search, and C-Means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state CA operations. It also uses a pipeline architecture for the hardware implementation of C-Means algorithm. The proposed architecture is embedded in a softcore CPU, and implemented on a field programmable logic array (FPGA) device for physical performance measurement. Experimental results show that the proposed architecture is an effective method for VQ optimization attaining both high performance and low computational time.

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