Abstract
A novel architecture for a hardware-based network intrusion detection system (NIDS) is presented in this paper. The system adopts an FPGA-based signature match co-processor as a core for the NIDS. The signature matcher is based on an algorithm that employs simple shift registers, or-gates, and ROMs in which patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of network intrusion detection.
| Original language | English |
|---|---|
| Title of host publication | Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings |
| Publisher | Springer Verlag |
| Pages | 776-784 |
| Number of pages | 9 |
| ISBN (Print) | 3540366792, 9783540366799 |
| Publication status | Published - 2006 Jan 1 |
| Event | International Conference on Embedded and Ubiquitous Computing, EUC 2006 - Seoul, Korea, Republic of Duration: 2006 Aug 1 → 2006 Aug 4 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 4096 LNCS |
| ISSN (Print) | 0302-9743 |
| ISSN (Electronic) | 1611-3349 |
Other
| Other | International Conference on Embedded and Ubiquitous Computing, EUC 2006 |
|---|---|
| Country | Korea, Republic of |
| City | Seoul |
| Period | 06/8/1 → 06/8/4 |
Fingerprint
ASJC Scopus subject areas
- Theoretical Computer Science
- Computer Science(all)
Cite this
Efficient logic circuit for network intrusion detection. / Roan, Huang Chun; Ou, Chien Min; Hwang, Wen Jyi; Lo, Chia Tien Dan.
Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings. Springer Verlag, 2006. p. 776-784 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4096 LNCS).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Efficient logic circuit for network intrusion detection
AU - Roan, Huang Chun
AU - Ou, Chien Min
AU - Hwang, Wen Jyi
AU - Lo, Chia Tien Dan
PY - 2006/1/1
Y1 - 2006/1/1
N2 - A novel architecture for a hardware-based network intrusion detection system (NIDS) is presented in this paper. The system adopts an FPGA-based signature match co-processor as a core for the NIDS. The signature matcher is based on an algorithm that employs simple shift registers, or-gates, and ROMs in which patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of network intrusion detection.
AB - A novel architecture for a hardware-based network intrusion detection system (NIDS) is presented in this paper. The system adopts an FPGA-based signature match co-processor as a core for the NIDS. The signature matcher is based on an algorithm that employs simple shift registers, or-gates, and ROMs in which patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of network intrusion detection.
UR - http://www.scopus.com/inward/record.url?scp=33746746555&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33746746555&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33746746555
SN - 3540366792
SN - 9783540366799
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 776
EP - 784
BT - Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings
PB - Springer Verlag
ER -