Abstract
A novel architecture for a hardware-based network intrusion detection system (NIDS) is presented in this paper. The system adopts an FPGA-based signature match co-processor as a core for the NIDS. The signature matcher is based on an algorithm that employs simple shift registers, or-gates, and ROMs in which patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of network intrusion detection.
| Original language | English |
|---|---|
| Title of host publication | Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings |
| Publisher | Springer Verlag |
| Pages | 776-784 |
| Number of pages | 9 |
| ISBN (Print) | 3540366792, 9783540366799 |
| Publication status | Published - 2006 Jan 1 |
| Event | International Conference on Embedded and Ubiquitous Computing, EUC 2006 - Seoul, Korea, Republic of Duration: 2006 Aug 1 → 2006 Aug 4 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 4096 LNCS |
| ISSN (Print) | 0302-9743 |
| ISSN (Electronic) | 1611-3349 |
Other
| Other | International Conference on Embedded and Ubiquitous Computing, EUC 2006 |
|---|---|
| Country | Korea, Republic of |
| City | Seoul |
| Period | 06/8/1 → 06/8/4 |
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ASJC Scopus subject areas
- Theoretical Computer Science
- Computer Science(all)
Cite this
Roan, H. C., Ou, C. M., Hwang, W. J., & Lo, C. T. D. (2006). Efficient logic circuit for network intrusion detection. In Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings (pp. 776-784). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4096 LNCS). Springer Verlag.