Efficient logic circuit for network intrusion detection

Huang Chun Roan, Chien Min Ou, Wen Jyi Hwang, Chia Tien Dan Lo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A novel architecture for a hardware-based network intrusion detection system (NIDS) is presented in this paper. The system adopts an FPGA-based signature match co-processor as a core for the NIDS. The signature matcher is based on an algorithm that employs simple shift registers, or-gates, and ROMs in which patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of network intrusion detection.

Original languageEnglish
Title of host publicationEmbedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings
PublisherSpringer Verlag
Pages776-784
Number of pages9
ISBN (Print)3540366792, 9783540366799
Publication statusPublished - 2006 Jan 1
EventInternational Conference on Embedded and Ubiquitous Computing, EUC 2006 - Seoul, Korea, Republic of
Duration: 2006 Aug 12006 Aug 4

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4096 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

OtherInternational Conference on Embedded and Ubiquitous Computing, EUC 2006
CountryKorea, Republic of
CitySeoul
Period06/8/106/8/4

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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  • Cite this

    Roan, H. C., Ou, C. M., Hwang, W. J., & Lo, C. T. D. (2006). Efficient logic circuit for network intrusion detection. In Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings (pp. 776-784). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4096 LNCS). Springer Verlag.