Efficient K-winner-take-all competitive learning hardware architecture for on-chip learning

Chien Min Ou, Hui Ya Li, Wen Jyi Hwang

Research output: Contribution to journalArticle

Abstract

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.

Original languageEnglish
Pages (from-to)11661-11683
Number of pages23
JournalSensors (Switzerland)
Volume12
Issue number9
DOIs
Publication statusPublished - 2012 Sep 1

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learning
hardware
education
chips
Learning
Hardware
Pipelines
field-programmable gate arrays
neurons
Neurons
Particle accelerators
Field programmable gate arrays (FPGA)
accelerators

Keywords

  • Competitive learning
  • FPGA
  • K-winners-take-all
  • Reconfigurable computing
  • System on programmable chip

ASJC Scopus subject areas

  • Analytical Chemistry
  • Biochemistry
  • Atomic and Molecular Physics, and Optics
  • Instrumentation
  • Electrical and Electronic Engineering

Cite this

Efficient K-winner-take-all competitive learning hardware architecture for on-chip learning. / Ou, Chien Min; Li, Hui Ya; Hwang, Wen Jyi.

In: Sensors (Switzerland), Vol. 12, No. 9, 01.09.2012, p. 11661-11683.

Research output: Contribution to journalArticle

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