Efficient K-means VLSI architecture for vector quantization

Hui Ya Li*, Wen Jyi Hwang, Chih Chieh Hsu, Chia Lung Hung

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)


A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.

Original languageEnglish
Title of host publicationImage Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings
Number of pages10
Publication statusPublished - 2009
Event16th Scandinavian Conference on Image Analysis, SCIA 2009 - Oslo, Norway
Duration: 2009 Jun 152009 Jun 18

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume5575 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other16th Scandinavian Conference on Image Analysis, SCIA 2009

ASJC Scopus subject areas

  • Theoretical Computer Science
  • General Computer Science


Dive into the research topics of 'Efficient K-means VLSI architecture for vector quantization'. Together they form a unique fingerprint.

Cite this