Efficient K-means VLSI architecture for vector quantization

Hui Ya Li; Wen Jyi Hwang; Chih Chieh Hsu; Chia Lung Hung

doi:10.1007/978-3-642-02230-2_45

Efficient K-means VLSI architecture for vector quantization

Hui Ya Li^*, Wen Jyi Hwang, Chih Chieh Hsu, Chia Lung Hung

^*Corresponding author for this work

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.

Original language	English
Title of host publication	Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings
Pages	440-449
Number of pages	10
DOIs	https://doi.org/10.1007/978-3-642-02230-2_45
Publication status	Published - 2009
Event	16th Scandinavian Conference on Image Analysis, SCIA 2009 - Oslo, Norway Duration: 2009 Jun 15 → 2009 Jun 18

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	5575 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Other

Other	16th Scandinavian Conference on Image Analysis, SCIA 2009
Country/Territory	Norway
City	Oslo
Period	2009/06/15 → 2009/06/18

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

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10.1007/978-3-642-02230-2_45

Cite this

Li, H. Y., Hwang, W. J., Hsu, C. C., & Hung, C. L. (2009). Efficient K-means VLSI architecture for vector quantization. In Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings (pp. 440-449). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 5575 LNCS). https://doi.org/10.1007/978-3-642-02230-2_45

Efficient K-means VLSI architecture for vector quantization. / Li, Hui Ya; Hwang, Wen Jyi; Hsu, Chih Chieh et al.
Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings. 2009. p. 440-449 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 5575 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, HY, Hwang, WJ, Hsu, CC & Hung, CL 2009, Efficient K-means VLSI architecture for vector quantization. in Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 5575 LNCS, pp. 440-449, 16th Scandinavian Conference on Image Analysis, SCIA 2009, Oslo, Norway, 2009/06/15. https://doi.org/10.1007/978-3-642-02230-2_45

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AB - A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.

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Efficient K-means VLSI architecture for vector quantization

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