Efficient K-means VLSI architecture for vector quantization

Hui Ya Li, Wen-Jyi Hwang, Chih Chieh Hsu, Chia Lung Hung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.

Original languageEnglish
Title of host publicationImage Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings
Pages440-449
Number of pages10
DOIs
Publication statusPublished - 2009 Nov 16
Event16th Scandinavian Conference on Image Analysis, SCIA 2009 - Oslo, Norway
Duration: 2009 Jun 152009 Jun 18

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume5575 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other16th Scandinavian Conference on Image Analysis, SCIA 2009
CountryNorway
CityOslo
Period09/6/1509/6/18

Fingerprint

VLSI Architecture
Vector Quantization
Vector quantization
K-means
Hardware Accelerator
Hardware Architecture
Performance Measurement
K-means Clustering
Centroid
Computer hardware
Field Programmable Gate Array
Particle accelerators
Program processors
Field programmable gate arrays (FPGA)
Partitioning
Hardware
Numerical Results
Costs
Architecture
Design

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

Cite this

Li, H. Y., Hwang, W-J., Hsu, C. C., & Hung, C. L. (2009). Efficient K-means VLSI architecture for vector quantization. In Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings (pp. 440-449). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 5575 LNCS). https://doi.org/10.1007/978-3-642-02230-2_45

Efficient K-means VLSI architecture for vector quantization. / Li, Hui Ya; Hwang, Wen-Jyi; Hsu, Chih Chieh; Hung, Chia Lung.

Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings. 2009. p. 440-449 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 5575 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, HY, Hwang, W-J, Hsu, CC & Hung, CL 2009, Efficient K-means VLSI architecture for vector quantization. in Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 5575 LNCS, pp. 440-449, 16th Scandinavian Conference on Image Analysis, SCIA 2009, Oslo, Norway, 09/6/15. https://doi.org/10.1007/978-3-642-02230-2_45
Li HY, Hwang W-J, Hsu CC, Hung CL. Efficient K-means VLSI architecture for vector quantization. In Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings. 2009. p. 440-449. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). https://doi.org/10.1007/978-3-642-02230-2_45
Li, Hui Ya ; Hwang, Wen-Jyi ; Hsu, Chih Chieh ; Hung, Chia Lung. / Efficient K-means VLSI architecture for vector quantization. Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings. 2009. pp. 440-449 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
@inproceedings{0d3c64980e3542db98a04c63d6afc059,
title = "Efficient K-means VLSI architecture for vector quantization",
abstract = "A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.",
author = "Li, {Hui Ya} and Wen-Jyi Hwang and Hsu, {Chih Chieh} and Hung, {Chia Lung}",
year = "2009",
month = "11",
day = "16",
doi = "10.1007/978-3-642-02230-2_45",
language = "English",
isbn = "3642022294",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
pages = "440--449",
booktitle = "Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings",

}

TY - GEN

T1 - Efficient K-means VLSI architecture for vector quantization

AU - Li, Hui Ya

AU - Hwang, Wen-Jyi

AU - Hsu, Chih Chieh

AU - Hung, Chia Lung

PY - 2009/11/16

Y1 - 2009/11/16

N2 - A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.

AB - A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.

UR - http://www.scopus.com/inward/record.url?scp=71049162164&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=71049162164&partnerID=8YFLogxK

U2 - 10.1007/978-3-642-02230-2_45

DO - 10.1007/978-3-642-02230-2_45

M3 - Conference contribution

AN - SCOPUS:71049162164

SN - 3642022294

SN - 9783642022296

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 440

EP - 449

BT - Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings

ER -