Efficient header classification architecture for network intrusion detection

Wen Jyi Hwang*, Chien Min Ou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


In this paper, an efficient FPGA-based header classification circuit is proposed for network intrusion detection system (NIDS). The circuit is based on simple shift registers and symbol encoders for the fast packet header classification in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.

Original languageEnglish
Pages (from-to)1839-1853
Number of pages15
JournalJournal of Information Science and Engineering
Issue number6
Publication statusPublished - 2009 Nov


  • FPGA implementation
  • Header classification architecture
  • Network intrusion detection system
  • Pattern matching
  • Shift-or algorithm

ASJC Scopus subject areas

  • Software
  • Human-Computer Interaction
  • Hardware and Architecture
  • Library and Information Sciences
  • Computational Theory and Mathematics


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