Efficient header classification architecture for network intrusion detection

Wen Jyi Hwang; Chien Min Ou

Efficient header classification architecture for network intrusion detection

Wen Jyi Hwang^*, Chien Min Ou

^*Corresponding author for this work

Department of Computer Science and Information Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, an efficient FPGA-based header classification circuit is proposed for network intrusion detection system (NIDS). The circuit is based on simple shift registers and symbol encoders for the fast packet header classification in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.

Original language	English
Pages (from-to)	1839-1853
Number of pages	15
Journal	Journal of Information Science and Engineering
Volume	25
Issue number	6
Publication status	Published - 2009 Nov

Keywords

FPGA implementation
Header classification architecture
Network intrusion detection system
Pattern matching
Shift-or algorithm

ASJC Scopus subject areas

Software
Human-Computer Interaction
Hardware and Architecture
Library and Information Sciences
Computational Theory and Mathematics

Cite this

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abstract = "In this paper, an efficient FPGA-based header classification circuit is proposed for network intrusion detection system (NIDS). The circuit is based on simple shift registers and symbol encoders for the fast packet header classification in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.",

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AB - In this paper, an efficient FPGA-based header classification circuit is proposed for network intrusion detection system (NIDS). The circuit is based on simple shift registers and symbol encoders for the fast packet header classification in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.

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KW - Network intrusion detection system

KW - Pattern matching

KW - Shift-or algorithm

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Efficient header classification architecture for network intrusion detection

Abstract

Keywords

ASJC Scopus subject areas

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