Efficient hardware architecture for kernel fuzzy c-means algorithm

Chien Min Ou, Wen Jyi Hwang, Ssu Min Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel VLSI architecture for kernel fuzzy c-means algorithm is presented in this paper. The architecture consists of efficient circuits for the computation of kernel functions, membership coefficients and cluster centers. In addition, the usual iterative operations for updating the membership matrix and cluster centers are merged into one single updating process to evade the large storage requirement. The circuit is used as a hardware accelerator of a softcore processor in a system-on-programmable chip for physical performance measurement. Experimental results show that the proposed solution is an effective alternative for cluster analysis with low computational cost and high performance.

Original languageEnglish
Title of host publicationInnovation for Applied Science and Technology
Pages3079-3086
Number of pages8
DOIs
Publication statusPublished - 2013 Feb 20
Event2nd International Conference on Engineering and Technology Innovation 2012, ICETI 2012 - Kaohsiung, Taiwan
Duration: 2012 Nov 22012 Nov 6

Publication series

NameApplied Mechanics and Materials
Volume284-287
ISSN (Print)1660-9336
ISSN (Electronic)1662-7482

Other

Other2nd International Conference on Engineering and Technology Innovation 2012, ICETI 2012
CountryTaiwan
CityKaohsiung
Period12/11/212/11/6

Keywords

  • FPGA
  • Fuzzy clustering
  • Reconfigurable computing
  • System-on-chip
  • VLSI

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Ou, C. M., Hwang, W. J., & Yang, S. M. (2013). Efficient hardware architecture for kernel fuzzy c-means algorithm. In Innovation for Applied Science and Technology (pp. 3079-3086). (Applied Mechanics and Materials; Vol. 284-287). https://doi.org/10.4028/www.scientific.net/AMM.284-287.3079