Efficient hardware architecture based on generalized Hebbian algorithm for texture classification

Shiow Jyu Lin, Yi Tsan Hung, Wen Jyi Hwang

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

The objective of this paper is to present an efficient hardware architecture for generalized Hebbian algorithm (GHA). In the architecture, the principal component computation and weight vector updating of the GHA are operated in parallel, so that the throughput of the circuit can be significantly enhanced. In addition, the weight vector updating process is separated into a number of stages for lowering area costs and increasing computational speed. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is designed. It is embedded in a system-on-programmable-chip (SOPC) platform for physical performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance and low area costs.

Original languageEnglish
Pages (from-to)3248-3256
Number of pages9
JournalNeurocomputing
Volume74
Issue number17
DOIs
Publication statusPublished - 2011 Oct 1

Keywords

  • Generalized hebbian algorithm
  • Principal component analysis
  • System-on-programmable-chip

ASJC Scopus subject areas

  • Computer Science Applications
  • Cognitive Neuroscience
  • Artificial Intelligence

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