Efficient architecture for spike sorting in reconfigurable hardware

Computer Science

• Hardware Implementation 100%
• Feature Extraction 100%
• Reconfigurable Hardware 100%
• Efficient Computation 50%
• Hardware Architecture 50%
• High Throughput 50%
• System on a Chip 50%
• Cluster Centroid 50%
• Mean Algorithm 50%
• Computer Hardware 50%
• Experimental Result 50%
• Storage Requirement 50%
• Field Programmable Gate Arrays 50%
• Principal Component 50%

INIS

• architecture 100%
• sorting 100%
• algorithms 83%
• fuzzy logic 66%
• calculation methods 50%
• performance 33%
• extraction 33%
• implementation 33%
• cost 33%
• operation 33%
• weight 16%
• design 16%
• vectors 16%
• employment 16%
• classification 16%
• iterative methods 16%
• storage 16%
• matrices 16%
• speed 16%