Efficient architecture for spike sorting in reconfigurable hardware

Wen-Jyi Hwang, Wei Hao Lee, Shiow Jyu Lin, Sheng Ying Lai

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

Original languageEnglish
Pages (from-to)14860-14887
Number of pages28
JournalSensors (Switzerland)
Volume13
Issue number11
DOIs
Publication statusPublished - 2013 Nov 1

Fingerprint

reconfigurable hardware
Reconfigurable hardware
classifying
Sorting
spikes
Cluster Analysis
hardware
Hardware
pattern recognition
Feature extraction
costs
systems-on-a-chip
Costs and Cost Analysis
field-programmable gate arrays
Networks (circuits)
centroids
Computer hardware
Field programmable gate arrays (FPGA)
Costs
platforms

Keywords

  • FPGA
  • Fuzzy C-means
  • Generalized Hebbian algorithm
  • Reconfigurable computing
  • Spike sorting
  • System-on-chip

ASJC Scopus subject areas

  • Analytical Chemistry
  • Atomic and Molecular Physics, and Optics
  • Biochemistry
  • Electrical and Electronic Engineering

Cite this

Efficient architecture for spike sorting in reconfigurable hardware. / Hwang, Wen-Jyi; Lee, Wei Hao; Lin, Shiow Jyu; Lai, Sheng Ying.

In: Sensors (Switzerland), Vol. 13, No. 11, 01.11.2013, p. 14860-14887.

Research output: Contribution to journalArticle

Hwang, Wen-Jyi ; Lee, Wei Hao ; Lin, Shiow Jyu ; Lai, Sheng Ying. / Efficient architecture for spike sorting in reconfigurable hardware. In: Sensors (Switzerland). 2013 ; Vol. 13, No. 11. pp. 14860-14887.
@article{de3bc46f645c46268f9b37d50526e54b,
title = "Efficient architecture for spike sorting in reconfigurable hardware",
abstract = "This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.",
keywords = "FPGA, Fuzzy C-means, Generalized Hebbian algorithm, Reconfigurable computing, Spike sorting, System-on-chip",
author = "Wen-Jyi Hwang and Lee, {Wei Hao} and Lin, {Shiow Jyu} and Lai, {Sheng Ying}",
year = "2013",
month = "11",
day = "1",
doi = "10.3390/s131114860",
language = "English",
volume = "13",
pages = "14860--14887",
journal = "Sensors (Switzerland)",
issn = "1424-3210",
publisher = "Multidisciplinary Digital Publishing Institute (MDPI)",
number = "11",

}

TY - JOUR

T1 - Efficient architecture for spike sorting in reconfigurable hardware

AU - Hwang, Wen-Jyi

AU - Lee, Wei Hao

AU - Lin, Shiow Jyu

AU - Lai, Sheng Ying

PY - 2013/11/1

Y1 - 2013/11/1

N2 - This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

AB - This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

KW - FPGA

KW - Fuzzy C-means

KW - Generalized Hebbian algorithm

KW - Reconfigurable computing

KW - Spike sorting

KW - System-on-chip

UR - http://www.scopus.com/inward/record.url?scp=84887348790&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84887348790&partnerID=8YFLogxK

U2 - 10.3390/s131114860

DO - 10.3390/s131114860

M3 - Article

VL - 13

SP - 14860

EP - 14887

JO - Sensors (Switzerland)

JF - Sensors (Switzerland)

SN - 1424-3210

IS - 11

ER -