Effect of contact-etch-stop-layer and Si1-xGex channel mechanical properties on nano-scaled short channel NMOSFETs with dummy gate arrays

Chang Chun Lee, Chuan Hsi Liu, Dian Yong Li, Chia Ping Hsieh

Research output: Contribution to journalArticlepeer-review


The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20 nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a + 3.0 GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100 nm gate width.

Original languageEnglish
Pages (from-to)230-234
Number of pages5
JournalMicroelectronics Reliability
Publication statusPublished - 2018 Apr 1


  • CESL
  • Dummy gate array
  • Finite element analysis
  • SiGe channel

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Safety, Risk, Reliability and Quality
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering


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