Direct Deposition of High-k van der Waals Dielectric for Top-Gated MoS₂ FETs Enabling Reconfigurable Logic and 2T0C DRAM toward BEOL-Compatible 3D Integration

Two-dimensional material-based FETs hold great promise but face significant challenges as a strong candidate for integration with Si-based devices in BEOL 3DICs. The fabrication process of top-gate dielectrics and the presence of dangling bonds are major factors that degrade channel transport and hinder VLSI. In this work, we successfully demonstrate top-gate MoS₂ MOSFET using PVD high-k vdW dielectric, Sb₂O₃. With EOT of 5.2 nm, the device achieves on/off ratio 10⁶ and D_it of 2×10¹¹ cm^-2eV^-1. By tuning the voltage ranges of the top gate and back gate, the transistor can operate under different logic gate configurations within each single device. Furthermore, two FETs are interconnected to form a 2T0C DRAM structure that exhibits memory retention under a 10 ms pulse operation. The use of inorganic oxide as high-k dielectric and the proposed 2T0C layout demonstrate strong potential for advancing 2D material applications in future manufacturing technologies.