Diode string with reduced clamping voltage for efficient on-chip ESD protection

Chun Yu Lin, Wei Hao Fu

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The standard steps of P- implantation and silicide block in the complementary metal-oxide semiconductor (CMOS) process are used in this design to implement the proposed diode string. The novel diode string realized by the diodes of P+ with N-well (P+/NW) and P- with N+ (P-/N+) is proposed in this letter. Besides, two diodes are merged together to form a silicon-controlled rectifier path to reduce the clamping voltage during electrostatic discharge (ESD) stress. The test devices of prior and proposed diode strings have been compared in a 0.18 μm CMOS process. With the higher current-handling ability and lower clamping voltage, the proposed diode string can be used as the efficient on-chip ESD protection device.

Original languageEnglish
Article number7588053
Pages (from-to)688-690
Number of pages3
JournalIEEE Transactions on Device and Materials Reliability
Volume16
Issue number4
DOIs
Publication statusPublished - 2016 Dec

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Keywords

  • Diode string
  • Electrostatic discharge (ESD)
  • Silicon-controlled rectifier (SCR)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

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