Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture

K. Y. Hsiang; C. Y. Liao; J. H. Liu; C. Y. Lin; J. Y. Lee; Z. F. Lou; F. S. Chang; W. C. Ray; Z. X. Li; H. C. Tseng; C. C. Wang; M. H. Liao; T. H. Hou; M. H. Lee

doi:10.1109/LED.2022.3204445

Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture

K. Y. Hsiang
, C. Y. Liao
, J. H. Liu
, C. Y. Lin
, J. Y. Lee
, Z. F. Lou
, F. S. Chang
, W. C. Ray
, Z. X. Li
, H. C. Tseng
, C. C. Wang
, M. H. Liao
, T. H. Hou
, M. H. Lee^*

^*Corresponding author for this work

Undergraduate Program of Electro-Optical Engineering

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

The 3D vertical ferroelectric tunneling junction (FTJ) of bilayer antiferroelectric (AFE) Hf_1-xZr_xO₂(HZO) and Al₂O₃ has been demonstrated for NAND-compatible feasibility. A bilayer-type FTJ is explored for the designs of the dielectric interlayer Al₂O₃ 0 nm to 4 nm and the ferroelectric type, while the current mechanism is revealed. The multilevel AFE-FTJ is exhibited for both the Program and Erase operations and realizes a synaptic device. High-density emerging memory and computing-in-memory (CiM) are in high demanded for the future era and can be feasible by the proposed vertical FTJ.

Original language	English
Pages (from-to)	1850-1853
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	43
Issue number	11
DOIs	https://doi.org/10.1109/LED.2022.3204445
Publication status	Published - 2022 Nov 1

Keywords

Ferroelectric
antiferroelectric

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/LED.2022.3204445

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Hsiang, K. Y., Liao, C. Y., Liu, J. H., Lin, C. Y., Lee, J. Y., Lou, Z. F., Chang, F. S., Ray, W. C., Li, Z. X., Tseng, H. C., Wang, C. C., Liao, M. H., Hou, T. H., & Lee, M. H. (2022). Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture. IEEE Electron Device Letters, 43(11), 1850-1853. https://doi.org/10.1109/LED.2022.3204445

Hsiang, KY, Liao, CY, Liu, JH, Lin, CY, Lee, JY, Lou, ZF, Chang, FS, Ray, WC, Li, ZX, Tseng, HC, Wang, CC, Liao, MH, Hou, TH & Lee, MH 2022, 'Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture', IEEE Electron Device Letters, vol. 43, no. 11, pp. 1850-1853. https://doi.org/10.1109/LED.2022.3204445

@article{9ee559336340465787f5fc7765e3be55,

title = "Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture",

abstract = "The 3D vertical ferroelectric tunneling junction (FTJ) of bilayer antiferroelectric (AFE) Hf1-xZrxO2(HZO) and Al2O3 has been demonstrated for NAND-compatible feasibility. A bilayer-type FTJ is explored for the designs of the dielectric interlayer Al2O3 0 nm to 4 nm and the ferroelectric type, while the current mechanism is revealed. The multilevel AFE-FTJ is exhibited for both the Program and Erase operations and realizes a synaptic device. High-density emerging memory and computing-in-memory (CiM) are in high demanded for the future era and can be feasible by the proposed vertical FTJ.",

keywords = "Ferroelectric, antiferroelectric",

author = "Hsiang, \{K. Y.\} and Liao, \{C. Y.\} and Liu, \{J. H.\} and Lin, \{C. Y.\} and Lee, \{J. Y.\} and Lou, \{Z. F.\} and Chang, \{F. S.\} and Ray, \{W. C.\} and Li, \{Z. X.\} and Tseng, \{H. C.\} and Wang, \{C. C.\} and Liao, \{M. H.\} and Hou, \{T. H.\} and Lee, \{M. H.\}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.",

year = "2022",

month = nov,

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doi = "10.1109/LED.2022.3204445",

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T1 - Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture

AU - Hsiang, K. Y.

AU - Liao, C. Y.

AU - Liu, J. H.

AU - Lin, C. Y.

AU - Lee, J. Y.

AU - Lou, Z. F.

AU - Chang, F. S.

AU - Ray, W. C.

AU - Li, Z. X.

AU - Tseng, H. C.

AU - Wang, C. C.

AU - Liao, M. H.

AU - Hou, T. H.

AU - Lee, M. H.

PY - 2022/11/1

Y1 - 2022/11/1

N2 - The 3D vertical ferroelectric tunneling junction (FTJ) of bilayer antiferroelectric (AFE) Hf1-xZrxO2(HZO) and Al2O3 has been demonstrated for NAND-compatible feasibility. A bilayer-type FTJ is explored for the designs of the dielectric interlayer Al2O3 0 nm to 4 nm and the ferroelectric type, while the current mechanism is revealed. The multilevel AFE-FTJ is exhibited for both the Program and Erase operations and realizes a synaptic device. High-density emerging memory and computing-in-memory (CiM) are in high demanded for the future era and can be feasible by the proposed vertical FTJ.

AB - The 3D vertical ferroelectric tunneling junction (FTJ) of bilayer antiferroelectric (AFE) Hf1-xZrxO2(HZO) and Al2O3 has been demonstrated for NAND-compatible feasibility. A bilayer-type FTJ is explored for the designs of the dielectric interlayer Al2O3 0 nm to 4 nm and the ferroelectric type, while the current mechanism is revealed. The multilevel AFE-FTJ is exhibited for both the Program and Erase operations and realizes a synaptic device. High-density emerging memory and computing-in-memory (CiM) are in high demanded for the future era and can be feasible by the proposed vertical FTJ.

KW - Ferroelectric

KW - antiferroelectric

UR - https://www.scopus.com/pages/publications/85137892974

UR - https://www.scopus.com/pages/publications/85137892974#tab=citedBy

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DO - 10.1109/LED.2022.3204445

M3 - Article

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SN - 0741-3106

VL - 43

SP - 1850

EP - 1853

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 11

ER -

Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture

Abstract

Keywords

ASJC Scopus subject areas

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