A new thinking has been spreading rapidly throughout the microelectronics community in the development and application of 3D stack package. Based on the concept, the application of the 3D stack package to high density memory modules makes DRAM provides major opportunities in both miniaturization and integration for advanced and portable electronic products. In order to meet the increasing demands for smaller, higher functionality-integrated and low cost package, this paper presents a packaging method for multi-chip IC without the problem of warpage and pin leakages. Multiple chips are packaged into a single package by stacking up the chips vertically, in which the packaging method is based on the standard wire bond technology with the use of longer bonding wire, appropriate epoxy for delamination and special care in wafer thinning. The presented method promotes the yield of the packaged IC and also successfully reduces the package size. However, special circuit techniques are required to maintain the normal operation of the packaged IC, as well as to maintain the compatible operating speed and power consumption. The reliability of the IC packaged with the presented method has been examined and it verifies the high performance of the presented method.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Safety, Risk, Reliability and Quality
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering