Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications

E. R. Hsieh, Y. S. Lin, Y. B. Zhao, C. H. Liu, C. H. Chien, Steve S. Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A new concept of the structure design with an alignment between the maximum band-to-band tunneling rate and electric field has been proposed to enhance the performance of TFETs. It was found that the specific gate of TFET to form an obtuse shape can dramatically improve the on-current of TFET, with over 4 order improvement in comparison to planar ones. This complementary TFET (CTFET) was also demonstrated by SRAM as a benchmark, with SiGe/Si integrated with III-V on Si substrate. In order to increase WNM and RSNM of CTFET SRAM, a new scheme has been adopted, in which SRAM has been successfully demonstrated with operating bias down to 0.3V.

Original languageEnglish
Title of host publication2015 Silicon Nanoelectronics Workshop, SNW 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863485389
Publication statusPublished - 2015 Sep 24
EventSilicon Nanoelectronics Workshop, SNW 2015 - Kyoto, Japan
Duration: 2015 Jun 142015 Jun 15

Publication series

Name2015 Silicon Nanoelectronics Workshop, SNW 2015

Conference

ConferenceSilicon Nanoelectronics Workshop, SNW 2015
CountryJapan
CityKyoto
Period15/6/1415/6/15

Fingerprint

Static random access storage
Electric fields
Substrates

Keywords

  • CMOS integrated circuits
  • Electric fields
  • Logic gates
  • Random access memory
  • Silicon
  • Silicon germanium
  • Tunneling

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Hsieh, E. R., Lin, Y. S., Zhao, Y. B., Liu, C. H., Chien, C. H., & Chung, S. S. (2015). Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications. In 2015 Silicon Nanoelectronics Workshop, SNW 2015 [7275322] (2015 Silicon Nanoelectronics Workshop, SNW 2015). Institute of Electrical and Electronics Engineers Inc..

Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications. / Hsieh, E. R.; Lin, Y. S.; Zhao, Y. B.; Liu, C. H.; Chien, C. H.; Chung, Steve S.

2015 Silicon Nanoelectronics Workshop, SNW 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7275322 (2015 Silicon Nanoelectronics Workshop, SNW 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hsieh, ER, Lin, YS, Zhao, YB, Liu, CH, Chien, CH & Chung, SS 2015, Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications. in 2015 Silicon Nanoelectronics Workshop, SNW 2015., 7275322, 2015 Silicon Nanoelectronics Workshop, SNW 2015, Institute of Electrical and Electronics Engineers Inc., Silicon Nanoelectronics Workshop, SNW 2015, Kyoto, Japan, 15/6/14.
Hsieh ER, Lin YS, Zhao YB, Liu CH, Chien CH, Chung SS. Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications. In 2015 Silicon Nanoelectronics Workshop, SNW 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7275322. (2015 Silicon Nanoelectronics Workshop, SNW 2015).
Hsieh, E. R. ; Lin, Y. S. ; Zhao, Y. B. ; Liu, C. H. ; Chien, C. H. ; Chung, Steve S. / Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications. 2015 Silicon Nanoelectronics Workshop, SNW 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 Silicon Nanoelectronics Workshop, SNW 2015).
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