TY - JOUR
T1 - Design of a 5.3-GHz 31.3-dBm Fully Integrated CMOS Power Amplifier Using Folded Splitting and Combining Architecture
AU - Tsai, Jeng Han
N1 - Funding Information:
Manuscript received September 16, 2018; revised December 21, 2018 and February 23, 2019; accepted March 12, 2019. Date of publication April 23, 2019; date of current version June 26, 2019. This work was supported the Ministry of Science and Technology of Taiwan under Contract MOST 105-2221-E-003-001-MY2 and Contract MOST 107-2221-E-003-003.
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - A transformer (TF)-based folded radial power splitting and binary power combining architecture is developed for fully integrated CMOS PA design in this paper. The proposed folded splitting and combining architecture has advantages of in-phase RF signal splitting/combining scheme, compact size, uniform dc distribution, and symmetric dc current supply/return path. A 5.3-GHz fully integrated PA using the developed splitting/combining architecture is fabricated on a standard 0.18- \mu \text{m} CMOS technology. The CMOS PA transmits saturation power ( P-{\mathrm {sat}} ) of 31.3 dBm, output 1-dB compression point (OP1 dB) of 26.1 dBm, and power added efficiency (PAE) of 22% at 5.3 GHz. The measured small signal gain is 18.3 dB at 5.3 GHz. The EVM has been measured with IEEE 802.11ac WLAN modulated signals. Using the 20-MHz bandwidth OFDM 64-QAM modulated signal, the PA meets the WLAN EVM specification of 5.6% up to 20.4-dBm linear output power. To our knowledge, the CMOS PA achieves the highest P-{\mathrm {sat}} and OP1 dB with decent PAE among other reported fully integrated CMOS PAs around 5 GHz to date.
AB - A transformer (TF)-based folded radial power splitting and binary power combining architecture is developed for fully integrated CMOS PA design in this paper. The proposed folded splitting and combining architecture has advantages of in-phase RF signal splitting/combining scheme, compact size, uniform dc distribution, and symmetric dc current supply/return path. A 5.3-GHz fully integrated PA using the developed splitting/combining architecture is fabricated on a standard 0.18- \mu \text{m} CMOS technology. The CMOS PA transmits saturation power ( P-{\mathrm {sat}} ) of 31.3 dBm, output 1-dB compression point (OP1 dB) of 26.1 dBm, and power added efficiency (PAE) of 22% at 5.3 GHz. The measured small signal gain is 18.3 dB at 5.3 GHz. The EVM has been measured with IEEE 802.11ac WLAN modulated signals. Using the 20-MHz bandwidth OFDM 64-QAM modulated signal, the PA meets the WLAN EVM specification of 5.6% up to 20.4-dBm linear output power. To our knowledge, the CMOS PA achieves the highest P-{\mathrm {sat}} and OP1 dB with decent PAE among other reported fully integrated CMOS PAs around 5 GHz to date.
KW - CMOS
KW - fully integration
KW - power amplifier (PA)
KW - power combining technique
KW - transformer (TF)
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U2 - 10.1109/TVLSI.2019.2908956
DO - 10.1109/TVLSI.2019.2908956
M3 - Article
AN - SCOPUS:85068208897
SN - 1063-8210
VL - 27
SP - 1527
EP - 1536
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 7
M1 - 8695840
ER -