Design and verification for dual issue digital signal processor

Cheng-Hung Lin, Chun Yu Lin, Shih Chieh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Digital Signal Processor (DSP) has been widely used in processing video and audio streaming data. Due to the huge amount of streaming data, increasing throughput is the key issue in designing DSP architecture. One way to increase the throughput of a DSP is to increase the instruction level parallelism. To increase the instruction level parallelism, many architectures have been proposed and can be classified into two main approaches, the superscaler and the VLIW architectures. Among the hardware architectures, the VLIW attracts a lot of attention due to its simple hardware complexity. However, the VLIW architecture suffers from the explosion of instruction memories due to the overhead of instruction grouping. In this paper, we propose a novel DSP architecture which contains three pipelines and performs dynamic instruction grouping by hardware. The experimental results show that our architecture can reduce 13% of memory requiremnt on average while maintaining the same performance.

Original languageEnglish
Title of host publication2009 International SoC Design Conference, ISOCC 2009
Pages536-539
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
Duration: 2009 Nov 222009 Nov 24

Publication series

Name2009 International SoC Design Conference, ISOCC 2009

Other

Other2009 International SoC Design Conference, ISOCC 2009
CountryKorea, Republic of
CityBusan
Period09/11/2209/11/24

Fingerprint

Digital signal processors
Very long instruction word architecture
Computer hardware
Audio streaming
Throughput
Data storage equipment
Video streaming
Explosions
Pipelines
Hardware
Processing

Keywords

  • DSP
  • Instruction level parallelism
  • Pipelines

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Lin, C-H., Lin, C. Y., & Chang, S. C. (2009). Design and verification for dual issue digital signal processor. In 2009 International SoC Design Conference, ISOCC 2009 (pp. 536-539). [5423829] (2009 International SoC Design Conference, ISOCC 2009). https://doi.org/10.1109/SOCDC.2009.5423829

Design and verification for dual issue digital signal processor. / Lin, Cheng-Hung; Lin, Chun Yu; Chang, Shih Chieh.

2009 International SoC Design Conference, ISOCC 2009. 2009. p. 536-539 5423829 (2009 International SoC Design Conference, ISOCC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lin, C-H, Lin, CY & Chang, SC 2009, Design and verification for dual issue digital signal processor. in 2009 International SoC Design Conference, ISOCC 2009., 5423829, 2009 International SoC Design Conference, ISOCC 2009, pp. 536-539, 2009 International SoC Design Conference, ISOCC 2009, Busan, Korea, Republic of, 09/11/22. https://doi.org/10.1109/SOCDC.2009.5423829
Lin C-H, Lin CY, Chang SC. Design and verification for dual issue digital signal processor. In 2009 International SoC Design Conference, ISOCC 2009. 2009. p. 536-539. 5423829. (2009 International SoC Design Conference, ISOCC 2009). https://doi.org/10.1109/SOCDC.2009.5423829
Lin, Cheng-Hung ; Lin, Chun Yu ; Chang, Shih Chieh. / Design and verification for dual issue digital signal processor. 2009 International SoC Design Conference, ISOCC 2009. 2009. pp. 536-539 (2009 International SoC Design Conference, ISOCC 2009).
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