Design and analysis of digital-assisted bandwidth-enhanced miller divider in 0.18-μm CMOS Process

Yen Hung Kuo; Jeng Han Tsai; Tian Wei Huang; Huei Wang

doi:10.1109/TMTT.2012.2218120

Design and analysis of digital-assisted bandwidth-enhanced miller divider in 0.18-μm CMOS Process

Yen Hung Kuo^*
, Jeng Han Tsai
, Tian Wei Huang
, Huei Wang

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

15 Citations (Scopus)

Abstract

A bandwidth-enhanced technique for a Miller divider is presented in this paper. The proposed frequency divider consists of a band-switched Miller divider and digital-assisted circuit to switch the resonator automatically. The proposed frequency divider is implemented in 0.18-μm CMOS technology and has a measured 57.4% bandwidth from 8.2 to 14.8 GHz at an input power of 0 dBm. The dc consumption is 12 mW. Compared to the previously reported Miller dividers, the proposed circuit achieves the widest fractional bandwidth.

Original language	English
Article number	6327626
Pages (from-to)	3769-3777
Number of pages	9
Journal	IEEE Transactions on Microwave Theory and Techniques
Volume	60
Issue number	12
DOIs	https://doi.org/10.1109/TMTT.2012.2218120
Publication status	Published - 2012

Keywords

CMOS
Miller divider
digital-assisted circuit
regenerative frequency divider

ASJC Scopus subject areas

Radiation
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/TMTT.2012.2218120

Cite this

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title = "Design and analysis of digital-assisted bandwidth-enhanced miller divider in 0.18-μm CMOS Process",

abstract = "A bandwidth-enhanced technique for a Miller divider is presented in this paper. The proposed frequency divider consists of a band-switched Miller divider and digital-assisted circuit to switch the resonator automatically. The proposed frequency divider is implemented in 0.18-μm CMOS technology and has a measured 57.4\% bandwidth from 8.2 to 14.8 GHz at an input power of 0 dBm. The dc consumption is 12 mW. Compared to the previously reported Miller dividers, the proposed circuit achieves the widest fractional bandwidth.",

keywords = "CMOS, Miller divider, digital-assisted circuit, regenerative frequency divider",

author = "Kuo, \{Yen Hung\} and Tsai, \{Jeng Han\} and Huang, \{Tian Wei\} and Huei Wang",

note = "Funding Information: Manuscript received March 30, 2012; revised August 22, 2012; accepted August 27, 2012. Date of publication October 09, 2012; date of current version December 13, 2012. This work was supported in part by the National Science Council (NSC) under Contract NSC101-2219-E-002-007, Contract NSC101-2219-E-002-008, Contract 101R89083, and Contract 101R8908.",

year = "2012",

doi = "10.1109/TMTT.2012.2218120",

language = "English",

volume = "60",

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AU - Tsai, Jeng Han

AU - Huang, Tian Wei

AU - Wang, Huei

N1 - Funding Information: Manuscript received March 30, 2012; revised August 22, 2012; accepted August 27, 2012. Date of publication October 09, 2012; date of current version December 13, 2012. This work was supported in part by the National Science Council (NSC) under Contract NSC101-2219-E-002-007, Contract NSC101-2219-E-002-008, Contract 101R89083, and Contract 101R8908.

PY - 2012

Y1 - 2012

N2 - A bandwidth-enhanced technique for a Miller divider is presented in this paper. The proposed frequency divider consists of a band-switched Miller divider and digital-assisted circuit to switch the resonator automatically. The proposed frequency divider is implemented in 0.18-μm CMOS technology and has a measured 57.4% bandwidth from 8.2 to 14.8 GHz at an input power of 0 dBm. The dc consumption is 12 mW. Compared to the previously reported Miller dividers, the proposed circuit achieves the widest fractional bandwidth.

AB - A bandwidth-enhanced technique for a Miller divider is presented in this paper. The proposed frequency divider consists of a band-switched Miller divider and digital-assisted circuit to switch the resonator automatically. The proposed frequency divider is implemented in 0.18-μm CMOS technology and has a measured 57.4% bandwidth from 8.2 to 14.8 GHz at an input power of 0 dBm. The dc consumption is 12 mW. Compared to the previously reported Miller dividers, the proposed circuit achieves the widest fractional bandwidth.

KW - CMOS

KW - Miller divider

KW - digital-assisted circuit

KW - regenerative frequency divider

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Design and analysis of digital-assisted bandwidth-enhanced miller divider in 0.18-μm CMOS Process

Abstract

Keywords

ASJC Scopus subject areas

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