Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC

Chieh Chen Ker; Chen Wei Hsu; Chun Yu Lin; Ming Dou Ker; Chun Chi Wang; Tsung Yin Chiang

doi:10.1109/VLSITSA64674.2025.11047198

Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC

Chieh Chen Ker
, Chen Wei Hsu
, Chun Yu Lin
, Ming Dou Ker
, Chun Chi Wang
, Tsung Yin Chiang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The additional N-well guard ring was often specified in the foundry's design rules to improve latch-up immunity of CMOS ICs. The impact of biasing the additional N-well guard ring on the latch-up immunity of a HV/LV mixed-voltage CMOS IC in a Bipolar-CMOS-DMOS (BCD) technology is investigated in this work. While intended to enhance latch-up immunity, an unexpected electrical overstress (EOS) failure is observed when the additional N-well guard ring is biased at low voltage during latch-up testing. Parasitic bipolar transistors between the high-voltage I/O devices and the additional N-well guard ring were activated to cause such an EOS failure. The effect of biasing the additional N-well guard rings on latch-up immunity is studied in detail through failure analysis.

Original language	English
Title of host publication	2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798331543129
DOIs	https://doi.org/10.1109/VLSITSA64674.2025.11047198
Publication status	Published - 2025
Externally published	Yes
Event	2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Hsinchu, Taiwan Duration: 2025 Apr 21 → 2025 Apr 24

Publication series

Name	2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers

Conference

Conference	2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025
Country/Territory	Taiwan
City	Hsinchu
Period	2025/04/21 → 2025/04/24

Keywords

additional guard ring
Electrical overstress (EOS)
latch-up test
mixed-voltage IC

ASJC Scopus subject areas

Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Signal Processing

Access to Document

10.1109/VLSITSA64674.2025.11047198

Cite this

Ker, C. C., Hsu, C. W., Lin, C. Y., Ker, M. D., Wang, C. C., & Chiang, T. Y. (2025). Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC. In 2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers (2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITSA64674.2025.11047198

Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC. / Ker, Chieh Chen; Hsu, Chen Wei; Lin, Chun Yu et al.
2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2025. (2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ker, CC, Hsu, CW, Lin, CY, Ker, MD, Wang, CC & Chiang, TY 2025, Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC. in 2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers. 2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers, Institute of Electrical and Electronics Engineers Inc., 2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025, Hsinchu, Taiwan, 2025/04/21. https://doi.org/10.1109/VLSITSA64674.2025.11047198

Ker CC, Hsu CW, Lin CY, Ker MD, Wang CC, Chiang TY. Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC. In 2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2025. (2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers). doi: 10.1109/VLSITSA64674.2025.11047198

Ker, Chieh Chen ; Hsu, Chen Wei ; Lin, Chun Yu et al. / Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC. 2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2025. (2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers).

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abstract = "The additional N-well guard ring was often specified in the foundry's design rules to improve latch-up immunity of CMOS ICs. The impact of biasing the additional N-well guard ring on the latch-up immunity of a HV/LV mixed-voltage CMOS IC in a Bipolar-CMOS-DMOS (BCD) technology is investigated in this work. While intended to enhance latch-up immunity, an unexpected electrical overstress (EOS) failure is observed when the additional N-well guard ring is biased at low voltage during latch-up testing. Parasitic bipolar transistors between the high-voltage I/O devices and the additional N-well guard ring were activated to cause such an EOS failure. The effect of biasing the additional N-well guard rings on latch-up immunity is studied in detail through failure analysis.",

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AB - The additional N-well guard ring was often specified in the foundry's design rules to improve latch-up immunity of CMOS ICs. The impact of biasing the additional N-well guard ring on the latch-up immunity of a HV/LV mixed-voltage CMOS IC in a Bipolar-CMOS-DMOS (BCD) technology is investigated in this work. While intended to enhance latch-up immunity, an unexpected electrical overstress (EOS) failure is observed when the additional N-well guard ring is biased at low voltage during latch-up testing. Parasitic bipolar transistors between the high-voltage I/O devices and the additional N-well guard ring were activated to cause such an EOS failure. The effect of biasing the additional N-well guard rings on latch-up immunity is studied in detail through failure analysis.

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Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC

Abstract

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Keywords

ASJC Scopus subject areas

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