Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems

Sung Chuan Fang, Kuo En Chang, Wu Shiung Feng, Sao Jie Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

A segment-crossing graph model is introduced, and a heuristic algorithm is proposed on the basis of this graph model. The algorithm is divided into two steps: Global Minimization and Local Minimization. In addition, practical considerations such as restricted terminals and adjacent limitations are addressed. The algorithm is evaluated by some routing examples using five layers. The results show that 45% of vias minimized are obtained on an average.

Original languageEnglish
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Pages60-65
Number of pages6
ISBN (Print)0818691492
Publication statusPublished - 1991 Jun 1
Externally publishedYes
EventProceedings of the 28th ACM/IEEE Design Automation Conference - San Francisco, CA, USA
Duration: 1991 Jun 171991 Jun 21

Other

OtherProceedings of the 28th ACM/IEEE Design Automation Conference
CitySan Francisco, CA, USA
Period91/6/1791/6/21

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Fang, S. C., Chang, K. E., Feng, W. S., & Chen, S. J. (1991). Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems. In Proceedings - Design Automation Conference (pp. 60-65). Publ by IEEE.