Compact FPGA implementation of 32-bits AES algorithm using block RAM

Chi Wu Huang*, Chi Jeng Chang, Mao Yuan Lin, Hung Yun Tai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)


Hardware implementation of Advanced Encryption Standard (AES) algorithm has been in intensive discussion since its first publication by National Institute of Standards and Technology (NIST) in 2000, especially in high throughput over 1 Giga bits per second (Gbps). However, the studies of low area, low power and low cost implementations, which usually have throughput less than 1Gbps and use the datapath less than 32-bit, have been appearing recently in ASIC as well as in FPGA for wireless communication and embedded hardware application. This paper proposes a 32-bit datapath implementation in small Xilinx FPGA Chip (Spartan-3 XC3S200). It uses 148 slice, 11 Block RAMs (BRAMs) and achieves the data stream of 647 Mega bits per second ( Mbps) at 287 MHz working frequency. It obtains 3.4 times improvement to the best known similar design in terms of ratio throughput per area (Throughput/Area), and 20% smaller in slice area.

Original languageEnglish
Title of host publicationTENCON 2007 - 2007 IEEE Region 10 Conference
Publication statusPublished - 2007
EventIEEE Region 10 Conference, TENCON 2007 - Taipei, Taiwan
Duration: 2007 Oct 302007 Nov 2

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON


OtherIEEE Region 10 Conference, TENCON 2007

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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