TY - JOUR
T1 - Compact ESD Protection Design for CMOS Low-Noise Amplifier
AU - Lin, Chun Yu
AU - Huang, Guo Lun
AU - Lin, Meng Ting
N1 - Funding Information:
Manuscript received August 19, 2019; revised October 13, 2019 and November 9, 2019; accepted November 18, 2019. Date of publication December 16, 2019; date of current version December 30, 2019. This work was supported in part by the Ministry of Science and Technology (MOST), Taiwan, under Contract MOST 108-2221-E-003-018. The review of this article was arranged by Editor C. Duvvury. (Corresponding author: Chun-Yu Lin.) The authors are with the Department of Electrical Engineering, National Taiwan Normal University, Taipei 106, Taiwan (e-mail: cy.lin@ieee.org).
Funding Information:
This work was supported in part by the Ministry of Science and Technology (MOST), Taiwan, under Contract MOST 108-2221-E-003-018.
Funding Information:
The authors would like to thank the Taiwan Semiconductor Research Institute (TSRI), Hsinchu, Taiwan, for the support of chip fabrication, Hanwa Electronic Ind. Company, Ltd., Ogaito, Wakayama, Japan, for setting up the electrostatic discharge (ESD) tester, and Prof. M.-D. Ker and his research group with National Chiao Tung University, Hsinchu, for their help during measurement.
Publisher Copyright:
© 1963-2012 IEEE.
PY - 2020/1
Y1 - 2020/1
N2 - A low-noise amplifier (LNA) is the input part of a radio frequency (RF) transceiver, which is vulnerable to electrostatic discharge (ESD). When ESD events occur, they may change the original characteristics of the LNA, such as gain decrease and noise figure (NF) increase. Dual diodes (DD) with MOS-based power clamp is a traditional on-chip ESD protection circuit, but it has disadvantages of large parasitic capacitance, large turn-on resistance, large layout area, and large leakage current. Therefore, a new compact ESD protection circuit is proposed, which uses stacked diodes with embedded silicon-controlled rectifier (SDeSCR) and SCR-based power clamp to protect the LNA. The proposed design has advantages of low parasitic capacitance, low clamping voltage, high ESD robustness, and compact layout area. In this work, the ESD protection circuit and the K-band LNA are fabricated in CMOS technology, and their RF characteristics and ESD robustness are verified.
AB - A low-noise amplifier (LNA) is the input part of a radio frequency (RF) transceiver, which is vulnerable to electrostatic discharge (ESD). When ESD events occur, they may change the original characteristics of the LNA, such as gain decrease and noise figure (NF) increase. Dual diodes (DD) with MOS-based power clamp is a traditional on-chip ESD protection circuit, but it has disadvantages of large parasitic capacitance, large turn-on resistance, large layout area, and large leakage current. Therefore, a new compact ESD protection circuit is proposed, which uses stacked diodes with embedded silicon-controlled rectifier (SDeSCR) and SCR-based power clamp to protect the LNA. The proposed design has advantages of low parasitic capacitance, low clamping voltage, high ESD robustness, and compact layout area. In this work, the ESD protection circuit and the K-band LNA are fabricated in CMOS technology, and their RF characteristics and ESD robustness are verified.
KW - Diode
KW - K-band
KW - electrostatic discharge (ESD)
KW - low-noise amplifier (LNA)
KW - silicon-controlled rectifier (SCR)
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U2 - 10.1109/TED.2019.2954739
DO - 10.1109/TED.2019.2954739
M3 - Article
AN - SCOPUS:85077817360
SN - 0018-9383
VL - 67
SP - 33
EP - 39
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 1
M1 - 8933353
ER -