Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

Li Wei Chu, Chun Yu Lin, Shiang Yu Tsai, Ming Dou Ker, Ming Hsiang Song, Chewn Pu Jou, Tse Hua Lu, Jen Chou Tseng, Ming Hsien Tsai, Tsun Lai Hsu, Ping Fang Hung, Tzu Heng Chang

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.

Original languageEnglish
Pages2127-2130
Number of pages4
DOIs
Publication statusPublished - 2012 Sep 28
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 2012 May 202012 May 23

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period12/5/2012/5/23

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Keywords

  • Electrostatic discharge (ESD)
  • V band
  • radio frequency (RF)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chu, L. W., Lin, C. Y., Tsai, S. Y., Ker, M. D., Song, M. H., Jou, C. P., Lu, T. H., Tseng, J. C., Tsai, M. H., Hsu, T. L., Hung, P. F., & Chang, T. H. (2012). Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. 2127-2130. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271706