Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

Li Wei Chu, Chun Yu Lin, Shiang Yu Tsai, Ming Dou Ker, Ming Hsiang Song, Chewn Pu Jou, Tse Hua Lu, Jen Chou Tseng, Ming Hsien Tsai, Tsun Lai Hsu, Ping Fang Hung, Tzu Heng Chang

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.

Original languageEnglish
Pages2127-2130
Number of pages4
DOIs
Publication statusPublished - 2012 Sep 28
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 2012 May 202012 May 23

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period12/5/2012/5/23

Fingerprint

Electrostatic discharge
Networks (circuits)
Low noise amplifiers
Frequency bands
Integrated circuits
Degradation
Silicon
Oxides

Keywords

  • Electrostatic discharge (ESD)
  • V band
  • radio frequency (RF)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chu, L. W., Lin, C. Y., Tsai, S. Y., Ker, M. D., Song, M. H., Jou, C. P., ... Chang, T. H. (2012). Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. 2127-2130. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271706

Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. / Chu, Li Wei; Lin, Chun Yu; Tsai, Shiang Yu; Ker, Ming Dou; Song, Ming Hsiang; Jou, Chewn Pu; Lu, Tse Hua; Tseng, Jen Chou; Tsai, Ming Hsien; Hsu, Tsun Lai; Hung, Ping Fang; Chang, Tzu Heng.

2012. 2127-2130 Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of.

Research output: Contribution to conferencePaper

Chu, LW, Lin, CY, Tsai, SY, Ker, MD, Song, MH, Jou, CP, Lu, TH, Tseng, JC, Tsai, MH, Hsu, TL, Hung, PF & Chang, TH 2012, 'Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology' Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of, 12/5/20 - 12/5/23, pp. 2127-2130. https://doi.org/10.1109/ISCAS.2012.6271706
Chu LW, Lin CY, Tsai SY, Ker MD, Song MH, Jou CP et al. Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. 2012. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271706
Chu, Li Wei ; Lin, Chun Yu ; Tsai, Shiang Yu ; Ker, Ming Dou ; Song, Ming Hsiang ; Jou, Chewn Pu ; Lu, Tse Hua ; Tseng, Jen Chou ; Tsai, Ming Hsien ; Hsu, Tsun Lai ; Hung, Ping Fang ; Chang, Tzu Heng. / Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of.4 p.
@conference{0fca9e21b5a64244aa3aa9f9cecfade7,
title = "Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology",
abstract = "Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.",
keywords = "Electrostatic discharge (ESD), V band, radio frequency (RF)",
author = "Chu, {Li Wei} and Lin, {Chun Yu} and Tsai, {Shiang Yu} and Ker, {Ming Dou} and Song, {Ming Hsiang} and Jou, {Chewn Pu} and Lu, {Tse Hua} and Tseng, {Jen Chou} and Tsai, {Ming Hsien} and Hsu, {Tsun Lai} and Hung, {Ping Fang} and Chang, {Tzu Heng}",
year = "2012",
month = "9",
day = "28",
doi = "10.1109/ISCAS.2012.6271706",
language = "English",
pages = "2127--2130",
note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

TY - CONF

T1 - Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

AU - Chu, Li Wei

AU - Lin, Chun Yu

AU - Tsai, Shiang Yu

AU - Ker, Ming Dou

AU - Song, Ming Hsiang

AU - Jou, Chewn Pu

AU - Lu, Tse Hua

AU - Tseng, Jen Chou

AU - Tsai, Ming Hsien

AU - Hsu, Tsun Lai

AU - Hung, Ping Fang

AU - Chang, Tzu Heng

PY - 2012/9/28

Y1 - 2012/9/28

N2 - Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.

AB - Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.

KW - Electrostatic discharge (ESD)

KW - V band

KW - radio frequency (RF)

UR - http://www.scopus.com/inward/record.url?scp=84866627421&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866627421&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271706

DO - 10.1109/ISCAS.2012.6271706

M3 - Paper

AN - SCOPUS:84866627421

SP - 2127

EP - 2130

ER -