CMOS oversampling Δ Σ magnetic to digital converters

Lee An Ho; Shr Lung Chen; Chien Hung Kuo; Shen Iuan Liu

doi:10.1109/ISCAS.2001.921874

CMOS oversampling Δ Σ magnetic to digital converters

Lee An Ho, Shr Lung Chen, Chien Hung Kuo, Shen Iuan Liu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this paper, a CMOS oversampling delta sigma (Δ Σ) magnetic to digital converter (MDC) is proposed. In the MDC, the magnetic operational amplifier (MOP) combines with the switched capacitor (SC) Δ Σ modulator, and converts the external magnetic field into digital form. Simulation and measurement results indicate that the average digital output versus the applied magnetic field is quite linear. The prototype circuit was fabricated in a 0.5 μm CMOS DPDM process. The circuit operates at a 5 V supply voltage and the sampling rate of 2.5 MHz. The maximum signal range of the converter is at least ±100 mT and the resolution can reach as small as 1 mT. The gain error within ±100 mT is less than 3%. The conversion gain is 1.327 mv/mT and the power consumption is 49.3 mW.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages	388-391
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2001.921874
Publication status	Published - 2001
Externally published	Yes
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 2001 May 6 → 2001 May 9

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	1

Other

Other	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	2001/05/06 → 2001/05/09

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISCAS.2001.921874

Cite this

Ho, L. A., Chen, S. L., Kuo, C. H., & Liu, S. I. (2001). CMOS oversampling Δ Σ magnetic to digital converters. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 388-391). Article 921874 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 1). https://doi.org/10.1109/ISCAS.2001.921874

CMOS oversampling Δ Σ magnetic to digital converters. / Ho, Lee An; Chen, Shr Lung; Kuo, Chien Hung et al.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 2001. p. 388-391 921874 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ho, LA, Chen, SL, Kuo, CH & Liu, SI 2001, CMOS oversampling Δ Σ magnetic to digital converters. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 921874, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 1, pp. 388-391, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 2001/05/06. https://doi.org/10.1109/ISCAS.2001.921874

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abstract = "In this paper, a CMOS oversampling delta sigma (Δ Σ) magnetic to digital converter (MDC) is proposed. In the MDC, the magnetic operational amplifier (MOP) combines with the switched capacitor (SC) Δ Σ modulator, and converts the external magnetic field into digital form. Simulation and measurement results indicate that the average digital output versus the applied magnetic field is quite linear. The prototype circuit was fabricated in a 0.5 μm CMOS DPDM process. The circuit operates at a 5 V supply voltage and the sampling rate of 2.5 MHz. The maximum signal range of the converter is at least ±100 mT and the resolution can reach as small as 1 mT. The gain error within ±100 mT is less than 3%. The conversion gain is 1.327 mv/mT and the power consumption is 49.3 mW.",

author = "Ho, {Lee An} and Chen, {Shr Lung} and Kuo, {Chien Hung} and Liu, {Shen Iuan}",

year = "2001",

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AU - Kuo, Chien Hung

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N2 - In this paper, a CMOS oversampling delta sigma (Δ Σ) magnetic to digital converter (MDC) is proposed. In the MDC, the magnetic operational amplifier (MOP) combines with the switched capacitor (SC) Δ Σ modulator, and converts the external magnetic field into digital form. Simulation and measurement results indicate that the average digital output versus the applied magnetic field is quite linear. The prototype circuit was fabricated in a 0.5 μm CMOS DPDM process. The circuit operates at a 5 V supply voltage and the sampling rate of 2.5 MHz. The maximum signal range of the converter is at least ±100 mT and the resolution can reach as small as 1 mT. The gain error within ±100 mT is less than 3%. The conversion gain is 1.327 mv/mT and the power consumption is 49.3 mW.

AB - In this paper, a CMOS oversampling delta sigma (Δ Σ) magnetic to digital converter (MDC) is proposed. In the MDC, the magnetic operational amplifier (MOP) combines with the switched capacitor (SC) Δ Σ modulator, and converts the external magnetic field into digital form. Simulation and measurement results indicate that the average digital output versus the applied magnetic field is quite linear. The prototype circuit was fabricated in a 0.5 μm CMOS DPDM process. The circuit operates at a 5 V supply voltage and the sampling rate of 2.5 MHz. The maximum signal range of the converter is at least ±100 mT and the resolution can reach as small as 1 mT. The gain error within ±100 mT is less than 3%. The conversion gain is 1.327 mv/mT and the power consumption is 49.3 mW.

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ER -

CMOS oversampling Δ Σ magnetic to digital converters

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