CMOS oversampling ΔΣ magnetic to digital converters

L. A. Ho; S. L. Chen; C. H. Kuo; S. I. Liu

doi:10.1109/ISCAS.2001.921874

CMOS oversampling ΔΣ magnetic to digital converters

L. A. Ho^*
, S. L. Chen
, C. H. Kuo
, S. I. Liu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this paper, a CMOS oversampling delta sigma (ΔΣ) magnetic to digital converter (MDC) is proposed. In the MDC, the magnetic operational amplifier (MOP) combines with the switched capacitor (SC) ΔΣ modulator, and converts the external magnetic field into digital form. Simulation and measurement results indicate that the average digital output versus the applied magnetic field is quite linear. The prototype circuit was fabricated in a 0.5um CMOS DPDM process. The circuit operates at a 5V supply voltage and the sampling rate of 2.5MHz. The maximum signal range of the converter is at least ±100mT and the resolution can reach as small as 1mT. The gain error within ±100mT is less than 3%. The conversion gain is 1.327mv/mT and the power consumption is 49.3mW.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	388-391
Number of pages	4
ISBN (Electronic)	9780780366855
ISBN (Print)	0780366859
DOIs	https://doi.org/10.1109/ISCAS.2001.921874
Publication status	Published - 2001
Externally published	Yes
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 2001 May 6 → 2001 May 9

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
ISSN (Print)	0271-4310

Conference

Conference	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	2001/05/06 → 2001/05/09

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2001.921874

Cite this

Ho, L. A., Chen, S. L., Kuo, C. H., & Liu, S. I. (2001). CMOS oversampling ΔΣ magnetic to digital converters. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 388-391). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2001.921874

CMOS oversampling ΔΣ magnetic to digital converters. / Ho, L. A.; Chen, S. L.; Kuo, C. H. et al.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2001. p. 388-391 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ho, LA, Chen, SL, Kuo, CH & Liu, SI 2001, CMOS oversampling ΔΣ magnetic to digital converters. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Proceedings - IEEE International Symposium on Circuits and Systems, vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 388-391, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 2001/05/06. https://doi.org/10.1109/ISCAS.2001.921874

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title = "CMOS oversampling ΔΣ magnetic to digital converters",

abstract = "In this paper, a CMOS oversampling delta sigma (ΔΣ) magnetic to digital converter (MDC) is proposed. In the MDC, the magnetic operational amplifier (MOP) combines with the switched capacitor (SC) ΔΣ modulator, and converts the external magnetic field into digital form. Simulation and measurement results indicate that the average digital output versus the applied magnetic field is quite linear. The prototype circuit was fabricated in a 0.5um CMOS DPDM process. The circuit operates at a 5V supply voltage and the sampling rate of 2.5MHz. The maximum signal range of the converter is at least ±100mT and the resolution can reach as small as 1mT. The gain error within ±100mT is less than 3\%. The conversion gain is 1.327mv/mT and the power consumption is 49.3mW.",

author = "Ho, \{L. A.\} and Chen, \{S. L.\} and Kuo, \{C. H.\} and Liu, \{S. I.\}",

year = "2001",

doi = "10.1109/ISCAS.2001.921874",

language = "English",

isbn = "0780366859",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "388--391",

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note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",

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AU - Ho, L. A.

AU - Chen, S. L.

AU - Kuo, C. H.

AU - Liu, S. I.

PY - 2001

Y1 - 2001

N2 - In this paper, a CMOS oversampling delta sigma (ΔΣ) magnetic to digital converter (MDC) is proposed. In the MDC, the magnetic operational amplifier (MOP) combines with the switched capacitor (SC) ΔΣ modulator, and converts the external magnetic field into digital form. Simulation and measurement results indicate that the average digital output versus the applied magnetic field is quite linear. The prototype circuit was fabricated in a 0.5um CMOS DPDM process. The circuit operates at a 5V supply voltage and the sampling rate of 2.5MHz. The maximum signal range of the converter is at least ±100mT and the resolution can reach as small as 1mT. The gain error within ±100mT is less than 3%. The conversion gain is 1.327mv/mT and the power consumption is 49.3mW.

AB - In this paper, a CMOS oversampling delta sigma (ΔΣ) magnetic to digital converter (MDC) is proposed. In the MDC, the magnetic operational amplifier (MOP) combines with the switched capacitor (SC) ΔΣ modulator, and converts the external magnetic field into digital form. Simulation and measurement results indicate that the average digital output versus the applied magnetic field is quite linear. The prototype circuit was fabricated in a 0.5um CMOS DPDM process. The circuit operates at a 5V supply voltage and the sampling rate of 2.5MHz. The maximum signal range of the converter is at least ±100mT and the resolution can reach as small as 1mT. The gain error within ±100mT is less than 3%. The conversion gain is 1.327mv/mT and the power consumption is 49.3mW.

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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PB - Institute of Electrical and Electronics Engineers Inc.

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ER -

CMOS oversampling ΔΣ magnetic to digital converters

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