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Characteristic Simulation of Hybrid Multilayer Junctionless Field Effect Transistors with Negative Capacitance Effect

  • Jun Ma
  • , Chien Liu
  • , Wei Dong Liu
  • , Yu Wen Hung
  • , Yu Chi Fan
  • , Hsiao Hsuan Hsu
  • , Zhi Wei Zheng*
  • , Chun Hu Cheng
  • *Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

In this study, we reported a hybrid multi-PNPN channel junctionless field effect transistor (JLFET) with negative capacitance (NC) effect by simulation. By incorporating a ferroelectric HfAlO capacitor with NC effect, an extremely low subthreshold swing of 34 mV/decade, a very high on/off current ratio and a very low driven voltage were achieved in the NC-enhanced hybrid multi-PNPN channel JLFET. This novel device not only improves the on-state current reduction while channel scaling down, but also shows great potential for the next-generation low-power three-dimensional stacked integrated circuit applications.

Original languageEnglish
Article number8946883
Pages (from-to)89-93
Number of pages5
JournalIEEE Transactions on Nanotechnology
Volume19
DOIs
Publication statusPublished - 2020

Keywords

  • Gate-all-around
  • junctionless
  • negative effect

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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