Abstract
Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.
Original language | English |
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Title of host publication | IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits |
DOIs | |
Publication status | Published - 2010 |
Externally published | Yes |
Event | 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 - Singapore, Singapore Duration: 2010 Jul 5 → 2010 Jul 9 |
Other
Other | 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 |
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Country | Singapore |
City | Singapore |
Period | 2010/07/05 → 2010/07/09 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering