CDM ESD protection design with initial-on concept in nanoscale CMOS process

Chun Yu Lin; Ming Dou Ker

doi:10.1109/IPFA.2010.5532223

CDM ESD protection design with initial-on concept in nanoscale CMOS process

Chun Yu Lin, Ming Dou Ker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.

Original language	English
Title of host publication	IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits
DOIs	https://doi.org/10.1109/IPFA.2010.5532223
Publication status	Published - 2010
Externally published	Yes
Event	17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 - Singapore, Singapore Duration: 2010 Jul 5 → 2010 Jul 9

Other

Other	17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010
Country	Singapore
City	Singapore
Period	2010/07/05 → 2010/07/09

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/IPFA.2010.5532223

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Lin, CY & Ker, MD 2010, CDM ESD protection design with initial-on concept in nanoscale CMOS process. in IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits., 5532223, 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010, Singapore, Singapore, 2010/07/05. https://doi.org/10.1109/IPFA.2010.5532223

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title = "CDM ESD protection design with initial-on concept in nanoscale CMOS process",

abstract = "Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.",

author = "Lin, {Chun Yu} and Ker, {Ming Dou}",

year = "2010",

doi = "10.1109/IPFA.2010.5532223",

language = "English",

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note = "17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 ; Conference date: 05-07-2010 Through 09-07-2010",

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AU - Lin, Chun Yu

AU - Ker, Ming Dou

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N2 - Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.

AB - Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.

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CDM ESD protection design with initial-on concept in nanoscale CMOS process

Abstract

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