Abstract
Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.
| Original language | English |
|---|---|
| Title of host publication | IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits |
| DOIs | |
| Publication status | Published - 2010 |
| Externally published | Yes |
| Event | 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 - Singapore, Singapore Duration: 2010 Jul 5 → 2010 Jul 9 |
Other
| Other | 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 |
|---|---|
| Country | Singapore |
| City | Singapore |
| Period | 10/7/5 → 10/7/9 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
CDM ESD protection design with initial-on concept in nanoscale CMOS process. / Lin, Chun Yu; Ker, Ming Dou.
IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits. 2010. 5532223.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - CDM ESD protection design with initial-on concept in nanoscale CMOS process
AU - Lin, Chun Yu
AU - Ker, Ming Dou
PY - 2010
Y1 - 2010
N2 - Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.
AB - Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.
UR - http://www.scopus.com/inward/record.url?scp=77956438525&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77956438525&partnerID=8YFLogxK
U2 - 10.1109/IPFA.2010.5532223
DO - 10.1109/IPFA.2010.5532223
M3 - Conference contribution
AN - SCOPUS:77956438525
SN - 9781424455973
BT - IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits
ER -