CDM ESD protection design with initial-on concept in nanoscale CMOS process

Chun Yu Lin, Ming Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.

Original languageEnglish
Title of host publicationIPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 - Singapore, Singapore
Duration: 2010 Jul 52010 Jul 9

Other

Other17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010
CountrySingapore
CitySingapore
Period10/7/510/7/9

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Lin, C. Y., & Ker, M. D. (2010). CDM ESD protection design with initial-on concept in nanoscale CMOS process. In IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits [5532223] https://doi.org/10.1109/IPFA.2010.5532223