C-slow retimed parallel histogram architectures for consumer imaging devices

Jose Cadenas, R. Sherratt, Pablo Huerta, Wen Chung Kao, Graham Megson

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.

Original languageEnglish
Article number6531108
Pages (from-to)291-295
Number of pages5
JournalIEEE Transactions on Consumer Electronics
Issue number2
Publication statusPublished - 2013


  • Digital Imaging
  • FPGA
  • Image Processing
  • Parallel Histograms
  • Pipelined Array

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering


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