Body effect of SiGe and CESL strained nano-node NMOSFETs on (100) silicon substrate

Mu Chun Wang, Guo Wei Wu, Shea Jue Wang, Hsin Chia Yang, Wen Shiang Liao, Ming Feng Lu, Jing Zong Jhang, Chuan Hsi Liu

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

An alternative technique to improve the electric performance of shrunk MOSFET devices is strained engineering. Considering SiGe channel layer as a global strain capping a Si layer to prevent Ge diffusion from the SiGe channel layer and soften the stress between SiON gate dielectric and SiGe channel is a possible way. To favor NMOSFET, depositing silicon nitride on gate as contact etching stop layer (CESL) process providing the tensile effect is more appreciated. In this study, besides the electrical characteristics with different strain processes, the conduction path and channel location of electron carrier through body bias adjustment is an attractive exploration. Because the charge profile in channel shown as a quantum mechanical effect is not a uniform distribution, the chief inversion layer thickness of electron carrier will be shifted when the substrate bias is applied. This evidence will be exhibited in gamma factor. Observing the gamma shift, the main conductive path of electron carrier can be diagnosed and analyzed about the quality of SiGe layer in growth.

Original languageEnglish
Pages379-382
Number of pages4
DOIs
Publication statusPublished - 2013 May 27
Event2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013 - Kaohsiung, Taiwan
Duration: 2013 Feb 252013 Feb 26

Other

Other2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013
CountryTaiwan
CityKaohsiung
Period13/2/2513/2/26

Keywords

  • CESL
  • Si-capping layer
  • global strain
  • substrate bias

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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