Block RAM based design of 8-bit AES operation modes

Chi Wu Huang; Hong You Chen; Hsing Chang Yeh; Chi Jeng Chang

doi:10.1016/j.proeng.2012.01.402

Block RAM based design of 8-bit AES operation modes

Chi Wu Huang, Hong You Chen^*, Hsing Chang Yeh, Chi Jeng Chang

^*Corresponding author for this work

Department of Industrial Education

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

8-bit AES implementation was first proposed in 2006 as Application Specific Instruction Processer (ASIP).[1] It featured in low area design, for the increasing popular applications in wireless and embedded devices, based on the stored-program concept which the software programs run in an FPGA processor. This paper presents a direct FPGA implementation, in which the circuit areas varied depend on the algorithms and the implementing methods used. Our specific 8-bit implementation using three Block RAMs (BRAMs) achieves 88 slices in CFB/OFB mode and 134 slices in ECB mode which are better than or very close to 122 slices achieved by ASIP. The throughputs over 31 Mega bit per second (Mbps) are at least 14 times higher than 2.18 Mbps achieved by ASIP.

Original language	English
Pages (from-to)	2848-2852
Number of pages	5
Journal	Procedia Engineering
Volume	29
DOIs	https://doi.org/10.1016/j.proeng.2012.01.402
Publication status	Published - 2012
Event	2012 International Workshop on Information and Electronics Engineering, IWIEE 2012 - Harbin, China Duration: 2012 Mar 10 → 2012 Mar 11

Keywords

AES
Block RAM(BRAM)
CFB
ECB
OFB

ASJC Scopus subject areas

Building and Construction
General Engineering

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10.1016/j.proeng.2012.01.402

Cite this

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title = "Block RAM based design of 8-bit AES operation modes",

abstract = "8-bit AES implementation was first proposed in 2006 as Application Specific Instruction Processer (ASIP).[1] It featured in low area design, for the increasing popular applications in wireless and embedded devices, based on the stored-program concept which the software programs run in an FPGA processor. This paper presents a direct FPGA implementation, in which the circuit areas varied depend on the algorithms and the implementing methods used. Our specific 8-bit implementation using three Block RAMs (BRAMs) achieves 88 slices in CFB/OFB mode and 134 slices in ECB mode which are better than or very close to 122 slices achieved by ASIP. The throughputs over 31 Mega bit per second (Mbps) are at least 14 times higher than 2.18 Mbps achieved by ASIP.",

keywords = "AES, Block RAM(BRAM), CFB, ECB, OFB",

author = "Huang, {Chi Wu} and Chen, {Hong You} and Yeh, {Hsing Chang} and Chang, {Chi Jeng}",

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language = "English",

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pages = "2848--2852",

journal = "Procedia Engineering",

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note = "2012 International Workshop on Information and Electronics Engineering, IWIEE 2012 ; Conference date: 10-03-2012 Through 11-03-2012",

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AU - Huang, Chi Wu

AU - Chen, Hong You

AU - Yeh, Hsing Chang

AU - Chang, Chi Jeng

PY - 2012

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N2 - 8-bit AES implementation was first proposed in 2006 as Application Specific Instruction Processer (ASIP).[1] It featured in low area design, for the increasing popular applications in wireless and embedded devices, based on the stored-program concept which the software programs run in an FPGA processor. This paper presents a direct FPGA implementation, in which the circuit areas varied depend on the algorithms and the implementing methods used. Our specific 8-bit implementation using three Block RAMs (BRAMs) achieves 88 slices in CFB/OFB mode and 134 slices in ECB mode which are better than or very close to 122 slices achieved by ASIP. The throughputs over 31 Mega bit per second (Mbps) are at least 14 times higher than 2.18 Mbps achieved by ASIP.

AB - 8-bit AES implementation was first proposed in 2006 as Application Specific Instruction Processer (ASIP).[1] It featured in low area design, for the increasing popular applications in wireless and embedded devices, based on the stored-program concept which the software programs run in an FPGA processor. This paper presents a direct FPGA implementation, in which the circuit areas varied depend on the algorithms and the implementing methods used. Our specific 8-bit implementation using three Block RAMs (BRAMs) achieves 88 slices in CFB/OFB mode and 134 slices in ECB mode which are better than or very close to 122 slices achieved by ASIP. The throughputs over 31 Mega bit per second (Mbps) are at least 14 times higher than 2.18 Mbps achieved by ASIP.

KW - AES

KW - Block RAM(BRAM)

KW - CFB

KW - ECB

KW - OFB

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Block RAM based design of 8-bit AES operation modes

Abstract

Keywords

ASJC Scopus subject areas

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